Mikhail Anatolievich Sotnikov

TL;DR: In this article, a channel routing method consisting of computing channel parameters (200), classifying a channel complexity and estimating a channel height (220), optionally, determining a trunk placement direction (225), assigning tracks and layers (230), determining a quality function QF (240), and optimizing (250).

TL;DR: In this article, a circuit layout representation is converted to a constraint graph representation in a reference direction and a critical path subgraph is constructed based upon the reference and orthogonal constraint graphs, where one or more critical paths are chosen as the longest paths between the source and sink vertices of the reference constraint graph.

TL;DR: Results using the proposed methodology shows that there are as much as ∼2X improvement in DFM-violation score in a 45nm technology library, and the total-net capacitance in the cells is reduced by as muchAs ∼2%.

TL;DR: In this article, a layout of a standard cell is created by prioritizing routability characteristics of the standard cell layout, so that the characteristics that are more likely to enhance routing efficiency are emphasized in the cell layout.

TL;DR: In this paper, a method for circuit layout migration comprises creating a list of layout components in a source layout, determining a plurality of first groups of layout component being regularly aligned horizontally or vertically, determining first subsets of layouts components which each belong to at least two of a respective set of determined first groups, each second subsets comprising mutually exclusive ones of the first layout components, determining symmetry axes for pairs of second groups, building a constraint graph of the layout components of the source layout using alignment constraints for the alignment of layouts within each of the second groups and distance constraints for preserving