Disclosed is a subgrid detailed router that performs searches for wire locations at the grid level. Once a solution is found, the wire is placed in a based upon a finer subgrid. Specifically, the present invention includes subgrids that in a preferred embodiment have a resolution that is 16X greater than the resolution of the conventional grids. This increased resolution is useful for improving routing density with variable width and variable spacing designs. In operation, the subgrid detailed router of the present invention searches at the grid level for potential wire paths using a code associated with each grid. This code contains data corresponding to each of the subgrids, such that upon completion of a routing a net, information exists that allows for the placement of the net at locations corresponding to the subgrid that has finer resolution than the grid which was used to implement the routing search. Thus, the present invention is as efficient as conventional grid based routers in finding an appropriate path.

Subgrid detailed routing

A CMOS active pixel sensor includes a photodiode, a transmitting transistor, a reset transistor, a fingered type source follower transistor and a selecting transistor, where the photodiode generates charge in response to incident light, the transmitting transistor transmits the charge stored in the photodiode to a sensing node, the reset transistor, coupled to a power supply voltage, resets a voltage of the sensing node so that the sensing node has substantially a level of the power supply voltage, the fingered type source follower transistor amplifies the voltage of the sensing node, the selecting transistor transmits a voltage of a source electrode of the fingered type source follower transistor into an internal circuit in response to a selection signal, thus, the channel width of the source follower transistor may be increased, and the MOS device noise due to the source follower transistor may be reduced.

CMOS active pixel sensor and active pixel sensor array using fingered type source follower transistor

An automated computer-implemented method, storage medium, and system for obtaining a pre-layout estimation of a characteristic of a standard cell including receiving a pre-layout netlist of a standard cell, applying at least one transformation to the pre-layout netlist to obtain an estimated representation, and characterizing the estimated representation to obtain a pre-layout estimation of the characteristic of the standard cell.

System and method for automated accurate pre-layout estimation of standard cell characteristics

A system and method for improving and optimizing current delivery into a chip, which is limited by the physical properties of the connections (e.g., Controlled Collapse Chip Connection or C4s). The system and method enables rapid C4 bump current estimation and placement including generating a one-time computed sensitivity matrix that includes all of the contributions of macros (or groups of components) to C4 current. The system and method further enables the calculation of a C4 current changes using the one-time computed sensitivity matrix and redistributed currents due to deletion of one or more C4 connectors. The system coupled with design and programming methodologies improve and optimize current delivery is extendable to connections across layers in a multilayer 3D chip stack.

Automating current-aware integrated circuit and package design and optimization

In some embodiments, in a method, cell layouts of a plurality of cells are received. For each cell, a respective constraint that affects a geometry of an interconnect to be coupled to an output pin of the cell in a design layout is determined based on a geometry of the output pin of the cell in the cell layout.

Electromigration-aware layout generation

A method, data processing system, and computer program product are provided for routing a circuit placement a number of times, resulting in a number of routings. An electromigration quality value is computed for each of the routings, and the routing with the best electromigration quality value is selected. In one embodiment, each routing is analyzed with attention to the current that passes through each of the routing's segments in order to compute a current distribution that is used to compute a routing quality vector. In another embodiment, multiple placements are generated and the electromigration placement quality vectors are computed for the various placements with the placement with the best electromigration quality vector being selected. In one embodiment, the placement with the best electromigration quality vector is routed the number of times to determine the routing with the lowest (best) electromigration quality value.

System and method for electromigration tolerant cell synthesis

Standard cells are basic building blocks, crucial for digital designs. Manufacturability improvements in standard cells have huge leverage, returning big benefits in yield and performance to all designs which may use them. Most of the benefits can be obtained by making changes to relatively few transistors in the cell, early in the design cycle. This paper presents a methodology to make standard cells more robust to manufacturing variations using DFM guidelines and knowledge of circuit performance sensitivity. Sensitivity analysis to variation parameters is performed to determine the critical cells and the critical transistors within those cells. Layout changes for DFM guidelines are performed selectively on the sensitive transistors within the cells. Results using the proposed methodology shows that there are as much as ∼2X improvement in DFM-violation score in a 45nm technology library. The proposed methodology also reduces the total-net capacitance in the cells by as much as ∼2%. These improvements are obtained without penalizing the cell area and cell pin-outs.

A sensitivity-aware methodology to improve cell layouts for DFM guidelines

A method for generating an integrated circuit layout is disclosed. One embodiment includes receiving an integrated circuit netlist describing a plurality of transistors and a plurality of conductors for interconnecting the plurality of transistors, each of the plurality of transistors having a width in a layout corresponding to the integrated circuit netlist. More than one of the plurality of transistors are determined to be the widest transistors, all having the same width. One of the widest transistors is folded to produce a folded transistor that is electrically equivalent to the widest transistor. The folded transistor has at least two fingers, each finger having a smaller width than the width of the widest transistors. A fold solution for the layout having the one folded transistor is created.

Method for automated transistor folding

A layout of a standard cell is created by prioritizing routability characteristics of the standard cell layout. The routability characteristics are prioritized so that the characteristics that are more likely to enhance routing efficiency are emphasized in the cell layout. The prioritization of the routability characteristics can be indicated by a set of weights, with each weight in the set indicating the priority of a corresponding routability characteristic of the standard cell layout. The weights can be used to calculate a weighted sum of the routability characteristics of the standard cell, thereby providing a way to efficiently compare the routability of different standard cell layouts.

Cell routability prioritization

A layout tool partially replicates the layout of a base cell to determine the layout for a target cell The base cell is information representing an arrangement of a set of transistors having an established layout The target cell is information indicating the desired arrangement of another set of transistors The layout tool identifies correspondences between subsets of the base cell transistors and subsets of the target cell transistors and replicates the layout of the identified base cell subsets to determine the layout for the identified target cell subsets In addition, the layout tool can identify base cell subsets that closely match target cell subsets, but for which the layout cannot be exactly replicated because of obstructions in the target cell subsets For such identified base cell subsets, the layout tool can determine a layout by adjusting the base cell subset layouts to avoid the obstructions

Vladimir P. Rozenfeld

Papers

System and method for electromigration tolerant cell synthesis

A sensitivity-aware methodology to improve cell layouts for DFM guidelines

Method for automated transistor folding

Cell routability prioritization

Transistor-level layout synthesis