R
Robert L. Maziasz
Researcher at Freescale Semiconductor
Publications - 11
Citations - 43
Robert L. Maziasz is an academic researcher from Freescale Semiconductor. The author has contributed to research in topics: Transistor & Routing (electronic design automation). The author has an hindex of 4, co-authored 11 publications receiving 43 citations.
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Patent
System and method for electromigration tolerant cell synthesis
Robert L. Maziasz,Vladimir P. Rozenfeld,Iouri G. Smirnov,Sergei V. Somov,Igor G. Topouzov,Lyudmila Zinchenko +5 more
TL;DR: In this article, a method, data processing system, and computer program product are provided for routing a circuit placement a number of times, resulting in the number of routings, and the routing with the best electromigration quality value is selected.
Proceedings ArticleDOI
A sensitivity-aware methodology to improve cell layouts for DFM guidelines
Savithri Sundareswaran,Robert L. Maziasz,Vladimir P. Rozenfeld,Mikhail Anatolievich Sotnikov,Mukhanov Konstantin +4 more
TL;DR: Results using the proposed methodology shows that there are as much as ∼2X improvement in DFM-violation score in a 45nm technology library, and the total-net capacitance in the cells is reduced by as muchAs ∼2%.
Patent
Method for automated transistor folding
Patrick McGuinness,Robert L. Maziasz,Andrei Zinchenko,Vladimir P. Rozenfeld,Michael Viacheslavovich Golikov,Alexander Mikhailovich Marchenko +5 more
TL;DR: In this article, a method for generating an integrated circuit layout is described, which includes a plurality of transistors and conductors for interconnecting the plurality, each of the transistors having a width in a layout corresponding to the integrated circuit netlist.
Patent
Cell routability prioritization
Robert L. Maziasz,Alexander Leonidovich Kerre,Vladimir P. Rozenfeld,Mikhail Anatolievich Sotnikov,Igor G. Topouzov +4 more
TL;DR: In this article, a layout of a standard cell is created by prioritizing routability characteristics of the standard cell layout, so that the characteristics that are more likely to enhance routing efficiency are emphasized in the cell layout.
Patent
Transistor-level layout synthesis
TL;DR: In this paper, a layout tool partially replicates the layout of a base cell to determine the layout for a target cell, but for which the layout cannot be exactly replicated because of obstructions in the target cell subsets.