Miltiadis Moralis-Pegios

TL;DR: It is demonstrated how optically-enabled eight-socket boards can be combined via a 256 × 256 Hipoλaos Optical Packet Switch into a powerful 256-node disaggregated system with less than 335 ns latency, forming a highly promising solution for the latency-critical rack-scale memory disaggregation era.

TL;DR: An optical switch architecture exploiting a hybrid broadcast-and-select/wavelength routing scheme with small-scale optical feedforward buffering is presented, reporting error-free performance with a power penalty of <2.5dB.

TL;DR: The Hipoλaos switch provides sub-μs latency and high throughput performance by utilizing distributed control and optical feed-forward buffering in a modified Spanke architecture and the architecture’s scalability up to 1024 × 1024 designs is discussed, along with a power consumption analysis and a roadmap toward an integrated version of the switch.

TL;DR: This paper reviews recent progress in integrated photonic neuromorphic architectures and analyzes the architectural and photonic hardware-based factors that limit their performance, and presents the approach towards transforming silicon coherent neuromorphic layouts into high-speed and high-accuracy Deep Learning (DL) engines by combining robust architectures with hardware-aware DL training.

TL;DR: Scale-up the Hipoλaos optical packet switch architecture to a thousand-port layout, at the same time upgrading its functionality to allow latency-free intra-tray multicasting, revealing up to 4250% throughput improvement, as compared to the conventional layout, while maintaining sub-μs latency.