Ming-Hsien Tu

TL;DR: This paper presents a novel single-ended disturb-free 9T subthreshold SRAM cell with cross-point data-aware Write word-line structure that facilitates bit-interleaving architecture and enhance soft error immunity by employing Error Checking and Correction (ECC) technique.

TL;DR: A new bit-interleaving 12T subthreshold SRAM cell with Data-Aware Power-Cutoff (DAPC) Write-assist to improve the Write-ability to mitigate increased device variations at low supply voltage under deep sub-100 nm processes is presented.

TL;DR: Asymmetrical Write-assist cell virtual ground biasing scheme and positive feedback sensing keeper schemes are proposed to improve the read static noise margin (RSNM), write margin (WM), and operation speed of a single-ended read/write 8 T SRAM cell.

TL;DR: This brief presents a two-port disturb-free 9T subthreshold static random access memory (SRAM) cell with independent single-ended read bitline and write bitline (WBL) and cross-point data-aware write structure to facilitate robust subth threshold operation and bit-interleaving architecture for enhanced soft error immunity.

TL;DR: The cross-point structure eliminates write half-select disturb to facilitate bit-interleaving architecture for enhanced soft error immunity and employs boosted word-line (WL) for improving both read performance and write-ability.