Showing papers by "Mohamed I. Elmasry published in 2007"

A 10dB 44GHz Loss-Compensated CMOS Distributed Amplifier

Abstract: An 8-stage distributed amplifier (DA) suitable for 40Gb/s optical communication is implemented in a 0.13mum CMOS process. The losses of on-chip transmission lines are compensated by active negative resistors. The DA achieves a flat gain of 10dB from DC to 44GHz with an input and output matching better than -8dB. The core DA and loss compensation circuitry dissipate 44mW and 59mW, respectively.

Impact of technology scaling on leakage reduction techniques

Abstract: Techniques that reduce total leakage in circuits operating in the active mode at different temperature conditions are examined. Also, the implications of technology scaling on the choice of techniques to mitigate total leakage are investigated. Logic gates in the 65 nm, 45 nm, and 32 nm nodes are simulated and analyzed. The techniques that are adopted for comparison in this work affect both gate and subthreshold leakage, namely, stack forcing, pin reordering, reverse body biasing, and high threshold voltage transistors. Aside from leakage, our analysis also highlights the impact of these techniques on the circuit's performance and noise margins. Power sensitive technology mapping tools can use the guidelines found in this work in the low power design flow, to meet the required maximum leakage current in a circuit. These guidelines are presented in general terms so that they can be adopted for any application and process technology.

A Timing-Driven Algorithm for Leakage Reduction in MTCMOS FPGAs

Abstract: A timing-driven MTCMOS (T-MTCMOS) CAD methodology is proposed for subthreshold leakage power reduction in nanometer FPGAs. The methodology uses the circuit timing information to tune the performance penalty due to sleep transistors according to the path delays, achieving an average leakage reduction of 44.36 % when applied to FPGA benchmarks using a CMOS 0.13mum process. Moreover, the methodology is applied to several FPGA architectures and CMOS technologies.

A Low-Power Multi-Pin Maze Routing Methodology

Abstract: As VLSI technologies scale into the deep submicron (DSM) realm, the minimum feature size continues to shrink. In contrast, the average die size is expected to remain constant or to slightly increase with each technology generation. This results in an average increase in the global interconnect lengths. In order to mitigate the impact of these global wires, buffer insertion is the most widely used technique. However, unconstrained buffering is bound to adversely affect the overall chip performance. In fact, the number of global interconnect buffers is expected to reach several hundreds of thousands to achieve an appropriate timing closure. This increase in buffers is destined to have a huge impact on the chip power consumption. In order to mitigate the impact of the power consumed by the interconnect buffers, a low power multi-pin routing methodology is proposed. The problem is tackled based on a graph theoretic representation of the interconnects that explores the various buffer sizing options in order to identify the lowest power path that can be assigned to the interconnect being routed. The formulation was found to be of a pseudo-polynomial complexity which fits well within the context of the increased number of buffers. The methodology is tested using the MCNC floorplan benchmarks to verify the correctness and the complexity. These tests showed that an average power saving as high as 45% with a 10% sacrifice in delay is observed

Leakage aware full adder cell

Abstract: In deep submicron technologies, static power dominates total power consumption. Introducing leakage awareness to the basic building blocks of parallel architectures is a decisive factor to cut off the leakage currents when appropriate. In this paper, a leakage awareness technique is applied to the full adder cell (FA) of an array multiplier. This reduces the leakage current of the FA cell by approximately 20%, assuming that the multiplier is continuously running and that the input bits have equal probabilities of occurrence.