Showing papers by "Mohamed I. Elmasry published in 2012"

Multi-Threshold CMOS Digital Circuits: Managing Leakage Power

Abstract: 1. Introduction.- References.- 2. Leakage Power: Challenges and Solutions.- 2.1 Introduction.- 2.2 Power Dissipation in CMOS Digital Circuits.- 2.3 Impact of Technology Scaling on Leakage Power.- 2.4 (Vdd-Vth) Design Space.- 2.5 Total Power Management.- 2.6 Leakage Power Control Circuit Techniques.- 2.7 Chapter Summary.- References.- 3. Embedded Mtcmos Combinational Circuits.- 3.1 Introduction.- 3.2 Basic Concept.- 3.3 The Power Minimization Problem.- 3.4 Algorithms.- 3.5 Choosing the High-Vth Value.- 3.6 Chapter Summary.- References.- 4. Mtcmos Combinational Circuits Using Sleep Transistors.- 4.1 Introduction.- 4.2 MTCMOS Design: Overview.- 4.3 Variable Breakpoint Switch Level Simulator [1].- 4.4 Hierarchical Sizing Based on Mutually Exclusive Discharge Patterns.- 4.5 Designing High-Vth Sleep Transistors, the Average Current Method [6].- 4.6 Drawbacks of Techniques.- 4.7 Distributed Sleep Transistors [9] [10].- 4.8 Clustering Techniques.- 4.9 Hybrid Heuristic Techniques.- 4.10 Virtual Ground Bounce.- 4.11 Results: Taking ground bounce into account.- 4.12 Power Management of Sleep Transistors.- 4.13 Chapter Summary.- References.- 5. Mtcmos Sequential Circuits.- 5.1 Introduction.- 5.2 MTCMOS Latch Circuit.- 5.3 MTCMOS Balloon Circuit.- 5.4 Intermittent Power Supply Scheme.- 5.5 Auto-Backgate-Controlled MTCMOS.- 5.6 Virtual Rails Clamp (VRC) Circuit.- 5.7 Leakage Sneak Paths in MTCMOS Sequential Circuits.- 5.8 Interfacing MTCMOS and CMOS blocks.- 5.9 Impact of the High-Vth and Low-Vth values on MTCMOS Sequential Circuit Design.- 5.10 Leakage Feedback Gates.- 5.11 Chapter Summary.- References.- 6. Mtcmos Dynamic Circuits.- 6.1 Introduction.- 6.2 Clock-Delayed Domino Logic: Overview.- 6.3 HS-Domino Logic.- 6.4 MTCMOS CD-Domino Logic: Analysis and Overview.- 6.5 MTCMOS HS-Domino (MHS-Domino) Logic.- 6.6 Domino Dual Cascode Voltage Switch Logic (DDCVSL).- 6.7 Chapter Summary.- References.- 7. Mtcmos Current-Steering Circuits.- 7.1 MOS Current Mode Logic: Overview.- 7.2 Introduction.- 7.3 Minimum Supply Voltage: First Constraint.- 7.4 Saturation Assurance: Second Constraint and the Proposed MTCMOS Design.- 7.5 A 2.5 Gbit/s 1:8 Demultiplexer in MTCMOS MCML.- 7.6 Impact of Using MTCMOS Technology Over MCML Parameters.- 7.7 Chapter Summary.- References.

NBTI and Process Variations Compensation Circuits Using Adaptive Body Bias

Abstract: Reliability and variability have become big design challenges facing submicrometer high-speed applications and microprocessors designers. A low area overhead adaptive body bias (ABB) circuit is proposed in this paper to compensate for negative-bias temperature instability (NBTI) aging and process variations to improve the system reliability and yield. The proposed ABB circuit consists of a threshold voltage-sensing circuit and an on-chip analog controller. In this paper, post-layout simulation results, referring to an industrial hardware-calibrated STMicroelectronics 65-nm CMOS technology transistor model, are presented. The transistor model contains process variations and NBTI aging model cards, which are declared by STMicroelectronics to be Silicon verified. Cadence RelXpert, Virtuoso Spectre, and Virtuoso UltraSim tools are used to estimate the NBTI aging and process variations impacts on a circuit block case study, extracted from a real microprocessor critical path. These results show that the proposed ABB compensates effectively for NBTI aging and process variations. For example, the proposed ABB improves the timing yield from 74.4% to 99.7% at zero aging time and from 36.6% to 97.1% at 10 years aging time. In addition, the proposed ABB increases the total yield from 67% to 99.5% at zero aging time and from 35.9% to 97.1% at 10 years aging time.

Advanced Low-Power Digital Circuit Techniques

Abstract: List of Figures. List of Tables. Preface. 1. Low-Power VLSI Design. 2. Low-Power High-Performance Adders. 3. Low-Power High-Performance Multipliers. 4. Low-Power Register File. 5. Low-Power Embedded BiCMOS/ECL SRAMs. 6. BiCMOS on-Chip Drivers. 7. Inter-Chip Low-Voltage Swing Transceivers. References. Index.

On-Chip Process Variations Compensation Using an Analog Adaptive Body Bias (A-ABB)

Abstract: An analog adaptive body bias (A-ABB) circuit is proposed in this paper. The A-ABB is used to compensate for die-to-die (D2D) and within-die (WID) parameter variations and accordingly, improves the circuit yield regarding the speed, the dynamic power, and the leakage power. The A-ABB consists of threshold voltage estimation circuits and analog control of the body bias performed by on-chip amplifier circuits. Circuit level simulation results of a circuit block case study, extracted from a real microprocessor critical path, referring to an industrial hardware-calibrated 65-nm CMOS technology transistor model, are demonstrated. This study shows that the proposed A-ABB reduces the standard deviations of the frequency, the dynamic power and the leakage power by factors of 6.6 X, 8.8 X, and 3.3 X, respectively, when both D2D and WID variations are considered. In addition, in this presented case study, initial total yields of 16.8% and 5.2% are improved to 99.9% and 84.1%, respectively. The advantage of the proposed A-ABB is its lower area overhead allowing it to be used at lower granularity level than that of the previously published ABB circuits.

High-Performance Digital VLSI Circuit Design

Abstract: From the Publisher: High-Performance Digital VLSI Circuit Design is devoted to the analysis and design of digital VLSI CMOS, bipolar and BiCMOS circuits which are optimized for high-performance applications The book starts by reviewing important background information in the area of MOS and bipolar device design and modeling Detailed analysis and design of high-performance CMOS, CML/ECL, NTL and BiCMOS circuits is given Achieving high-speed while maintaining low-power dissipation in digital circuits is addressed in depth in separate chapters The book ends with a sample application area of high-performance design; namely the design of phase-locked loops The book can be used as a reference for practicing IC designers and as a text for graduate and senior undergraduate students in the area of digital IC design