Heat and fluid flow in high-power LED packaging and applications

In this paper, a careful theoretical analysis of the thermal dynamics of an electronic device and its package was carried out in order to study the problem of the equivalent thermal circuit implementation. It was found that the device temperature evolution in time is ruled by an infinite and convergent series of time constants. The knowledge of the first n terms of the time-constant spectrum obtained from the temperature transient measurements allows the complete characterization of a suitable and reliable equivalent thermal circuit structured as a Cauer low-pass network with n cells. The total thermal resistance is therefore evaluated as a sum of several contributions due to given parts of the whole system. The techniques allowing the physical identifications of these contributions are also discussed. Furthermore, the influence of plastic coverage on the device thermal behavior is taken into account. The proposed characterization method is also applied to one-dimensional (1-D) multilayered simulated structures in order to study the influence of the number of time constants used for the analysis and effects of local defects or modifications of the material thermal properties.

Thermal resistance analysis by induced transient (TRAIT) method for power electronic devices thermal characterization. I. Fundamentals and theory

For pt.I see ibid., vol.13, no.6, p.1208-19 (1998). The TRAIT method for thermal characterization of electronic devices, whose theory was exposed in part I for one-dimensional (1-D) structures, was here applied to systems having heat fluxes with three-dimensional (3-D) dependence in order to demonstrate that the spatial resolution of the thermal resistance analysis is still qualitatively maintained in this type of structure too. The analytical procedure was first applied to simulated structures whose temperature transients and steady-state fields were obtained by means of a finite-element thermal simulation program. In these cases, the knowledge of the steady-state temperature distribution allowed identifying the thermal physical domains which correspond to the cells of the calculated equivalent thermal circuit composed by resistances and capacitances. Furthermore, some experiments on real electronic devices with purposely designed assembling structures were exposed and discussed. The samples were power-integrated circuits with plastic packages mounted on various substrates and Schottky diodes in TO-3 packages. The experiments on both simulated and real devices demonstrated that TRAIT analysis, being able to recognize the localization of some induced defects, maintains its spatial resolution character, despite the large distortion of the thermal domains occurring when the defects are close to the heat source.

Thermal resistance analysis by induced transient (TRAIT) method for power electronic devices thermal characterization. II. Practice and experiments

A mathematical model of the transient temperature response of integrated devices is presented which takes into account the three-dimensional (3-D) nature of heat flow and the physical structure of the device. Simple analytical relations for the transient thermal impedance and thermal time constants are derived for the first time. The impact of device geometry on the transient thermal response curve is discussed, and simple guidelines for the thermal design of solid-state devices operated in transient or pulsed regime are given.

On the modeling of the transient thermal behavior of semiconductor devices

This paper discusses some limitations in the approaches commonly adopted for device and circuit electro-thermal simulation Thermal models for circuit simulation assume a simple geometry for the region where power dissipation occurs Available models are compared The impact of model parameters and bias condition on simulation accuracy is discussed A new approach for calculating the temperature distribution under both steady-state and transient conditions is also proposed The accuracy of two-dimensional (2D) electro-thermal device simulations is then investigated It is shown that 2D simulations can lead to markedly inaccurate results Possible approaches to overcome these limitations are discussed

A critical review of thermal models for electro-thermal simulation

Since power densities in integrated circuits and power semiconductor devices are continuously increasing due to miniaturization of circuitry, the design of optimum heat spreaders and heat sinks for these applications requires rather sophisticated calculational methods. The chips and spreaders are usually rectangular in shape and although the problem is three-dimensional in nature, it is usually approximated by two-dimensional configurations. Steady-state and transient analytic solutions are presented for the axisymmetric, two-dimensional, and three-dimensional spreader geometries, which can be used to calculate the thermal resistance of the base alone. To determine the thermal resistance of the chip-base combination, the one-dimensional chip thermal resistance should be added to that of the base. These analytic solutions provide calculational means which are easier than the numerical methods. The exact analytic steady-state and transient solutions developed for the axisymmetric, two-dimensional, and three-dimensional configurations are in excellent agreement with the numerical calculations. The parametric calculations provide information on the important guidelines that a packaging engineer should bear in mind while designing and optimizing heat spreaders for power semiconductor applications. These points can be summarized as follows: 1) for a given chip area there exists an optimal base area, 2) increasing the base thickness initially decreases the thermal resistance and beyond a certain limit the latter increases with base thickness, and 3) the convective heat transfer coefficient strongly affects the thermal resistance and the usual assumption of an isothermal base is not always appropriate.

N. Abuaf

Papers

An analysis of the thermal response of power chip packages