Preface. 1. Introduction. 2. Optical Fiber. 3. Photodetectors. 4. Receiver Fundamentals. 5. Transimpledance Amplifiers. 6. Main Amplifiers. 7. Optical Transmitters. 8. Laser and Modulator Drivers. Appendix A: Eye Diagrams. Appendix B: Differential Circuits. Appendix C: S Parameters. Appendix D: Transistors and Technologies. Appendix E: Answers to the Problems. Appendix F: Notation. Appendix G: Symbols. Appendix H: Acronyms. References. Index.

Broadband Circuits for Optical Fiber Communication

The ability to produce a high-performance monolithic CMOS photoreceiver, including the photodetector, could enable greater use of optics in short-distance communication systems. Such a receiver requires the ability to simultaneously produce a photodetector compatible with a high-volume high-yield CMOS process, as well as the entire receiver circuit. The quest for this element has yet to produce a clear winner, and has proven quite challenging. We review some of the work in this field with the goal of informing the reader as to the origin of the challenges and the implementation tradeoffs. Finally, we report experimental results from a monolithic CMOS photoreceiver realized in a 0.35-/spl mu/m production CMOS process, including a CMOS photodiode. Operating at 1 Gb/s, the receiver requires an average input power of -6.3 dBm at 850 nm to obtain a measured bit error rate of 1/spl times/10/sup -9/, and dissipates 1.5 mW at 2.2 V, increasing to 6 mW at 3.3 V.

1-Gb/s integrated optical detectors and receivers in commercial CMOS technologies

Line-of-sight free-space optical links can provide extremely high bandwidth communications, but this usually requires that transmitter and receiver are precisely aligned. In order to allow terminals to be mobile, links must be able to track users within their field of view so that the link is maintained. There are various means to do this, but all require complex subsystems with a number of different optical, optoelectronic, and electrical components. A solid-state tracking architecture is introduced and a seven-channel tracking system demonstration described. The system is designed to operate at 155 Mb/s and is, to the best of our knowledge, the first that uses an integrated approach. Arrays of novel resonant cavity LED (RCLED) emitters that operate at 980 nm are used as sources. These are flip-chip bonded to arrays of CMOS driver circuits and integrated with the necessary transmitter optics. The receiver uses a back-illuminated detector array flip-chip bonded to arrays of custom CMOS receivers. All these components are custom and have performance substantially better than nonoptimized commercially available components. In the paper, the design and fabrication of the optics, optoelectronics, and electronics required for this is described. Successful operation of all the subsystems is detailed, together with results from an initial link demonstration.

Integrated transceivers for optical wireless communications

This paper presents a burst-mode receiver for 1.25-Gb/s Ethernet PON system using mixed-mode CMOS 0.18-/spl mu/m technology. With the modified cell-based AGC function and differential feed-forward topology, the receiver achieves sensitivity of -26.4 dBm, overload of -5.4 dBm, and a loud/soft ratio of 21 dB while keeping the low-voltage positive emitter-coupled logic (LVPECL) differential output level fully compliant with the ethernet passive optical network (EPON) standard. Unlike other burst-mode receivers, the design obtains fast response even without a reset signal from the network layer by creating a reset signal internally based on the incoming signal. This setting allows for simple system design. The overall architecture and several blocks are optimized in accordance with internal reset creation. Minimum guard time and preamble time are 250 and 50 ns, respectively; all timing parameters are better than the current EPON standard. The prototype contains all components on-chip that occupies 0.9/spl times/1.9 mm/sup 2/ and consumes 160 mA current from a 3.3-V supply.

A burst-mode receiver for 1.25-Gb/s ethernet PON with AGC and internally created reset signal

The burst-mode 3R receiver using monolithic ICs for 10-Gbit/s-class optical access networks is reported. In a point-to-multipoint access system like a passive optical network (PON), the receiver at the optical line terminal (OLT) must be able to handle burst-mode optical packets with significantly different powers and phases. An OLT receiver with high sensitivity with instantaneous response to burst inputs is desired for widening the accommodation area and for high efficiency in PON uplinks. Currently, the diffusion of high-speed Internet connection services represented by fiber to the home services at 1.25 Gbit/s is remarkable and the standardization of the next-generation system operating at 10 Gbit/s has started in IEEE. We first discuss the issues in the implementation of 10-Gbit/s-class PON systems, focusing on securing the accommodation area and the quality of the service comparable with those of the deployed system. Against that background, we propose target specifications for sensitivity, a dynamic range and response speed of the 10-Gbit/s-class burst-mode receiver so as to secure the power budget and the upstream efficiency comparable with those of the already-installed systems. Our burst-mode 3R receiver was designed to meet the above requirements and developed using monolithic ICs of transimpedance amplifier, limiting amplifier, and clock and data recovery circuit fabricated by using SiGe BiCMOS technologies along with a p-i-n photodiode. High sensitivity of , a wide dynamic range of over 16.5 dB, and quick response time of 75 ns were confirmed for burst inputs with extremely different powers.

A Burst-Mode 3R Receiver for 10-Gbit/s PON Systems With High Sensitivity, Wide Dynamic Range, and Fast Response

In a point-to-multipoint fiber-optic subscriber system using TDMA (time division multiple access), the receiver should be able to handle burst-data packets with different amplitudes, Moreover, high-bit-rate operation is desired for multimedia communications. The operational speed is mainly restricted by the input parasitic capacitance of the preamplifier. Reducing the input impedance of the preamplifier widens its frequency bandwidth, and it makes high-speed operation possible. A multistaged preamplifier using feedforward phase compensation technique has been devised for small input impedance with stable operation at high frequency. Multistaged feedforward bias control is used for quick response to burst data, and the time constant is also reduced for high-speed operation. Using these design techniques, an optical receiver IC was fabricated using standard 0.5-/spl mu/m CMOS technology. The instantaneous response receiver has high sensitivity of -35.6 dBm, a wide dynamic range of more than 26 dB for burst-mode optical input at 156 Mb/s, and requires no external adjustment. The use of standard CMOS technology and the freedom from external adjustment make it possible to build an inexpensive receiver module.

N. Ishihara

Papers

A 156-Mb/s CMOS optical receiver for burst-mode transmission