Showing papers in "IEEE Journal of Solid-state Circuits in 1998"

A general theory of phase noise in electrical oscillators

Abstract: A general model is introduced which is capable of making accurate, quantitative predictions about the phase noise of different types of electrical oscillators by acknowledging the true periodically time-varying nature of all oscillators. This new approach also elucidates several previously unknown design criteria for reducing close-in phase noise by identifying the mechanisms by which intrinsic device noise and external noise sources contribute to the total phase noise. In particular, it explains the details of how 1/f noise in a device upconverts into close-in phase noise and identifies methods to suppress this upconversion. The theory also naturally accommodates cyclostationary noise sources, leading to additional important design insights. The model reduces to previously available phase noise models as special cases. Excellent agreement among theory, simulations, and measurements is observed.

On-chip spiral inductors with patterned ground shields for Si-based RF ICs

Abstract: This paper presents a patterned ground shield inserted between an on-chip spiral inductor and silicon substrate. The patterned ground shield can be realized in standard silicon technologies without additional processing steps. The impacts of shield resistance and pattern on inductance, parasitic resistances and capacitances, and quality factor are studied extensively. Experimental results show that a polysilicon patterned ground shield achieves the most improvement. At 1-2 GHz, the addition of the shield increases the inductor quality factor up to 33% and reduces the substrate coupling between two adjacent inductors by as much as 25 dB. We also demonstrate that the quality factor of a 2-GHz LC tank can be nearly doubled with a shielded inductor.

Analysis, design, and optimization of spiral inductors and transformers for Si RF ICs

Abstract: Silicon integrated circuit spiral inductors and transformers are analyzed using electromagnetic analysis. With appropriate approximations, the calculations are reduced to electrostatic and magnetostatic calculations. The important effects of substrate loss are included in the analysis. Classic circuit analysis and network analysis techniques are used to derive two-port parameters from the circuits. From two-port measurements, low-order, frequency-independent lumped circuits are used to model the physical behavior over a broad-frequency range. The analysis is applied to traditional square and polygon inductors and transformer structures as well as to multilayer metal structures and coupled inductors. A custom computer-aided-design tool called ASITIC is described, which is used for the analysis, design, and optimization of these structures. Measurements taken over a frequency range from 100 MHz to 5 GHz show good agreement with theory.

Self-powered signal processing using vibration-based power generation

Abstract: Low power design trends raise the possibility of using ambient energy to power future digital systems. A chip has been designed and tested to demonstrate the feasibility of operating a digital system from power generated by vibrations in its environment. A moving coil electromagnetic transducer was used as a power generator. Calculations show that power on the order of 400 /spl mu/W can be generated. The test chip integrates an ultra-low power controller to regulate the generator voltage using delay feedback techniques, and a low power subband filter DSP load circuit. Tests verify 500 kHz self-powered operation of the subband filter, a level of performance suitable for sensor applications. The entire system, including the DSP load, consumes 18 /spl mu/W of power. The chip is implemented in a standard 0.8 /spl mu/m CMOS process. A single generator excitation produced 23 ms of valid DSP operation at a 500 kHz clock frequency, corresponding to 11,700 cycles.

A low-voltage, low quiescent current, low drop-out regulator

Abstract: The demand for low-voltage, low drop-out (LDO) regulators is increasing because of the growing demand for portable electronics, i.e., cellular phones, pagers, laptops, etc. LDO's are used coherently with dc-dc converters as well as standalone parts. In power supply systems, they are typically cascaded onto switching regulators to suppress noise and provide a low noise output. The need for low voltage is innate to portable low power devices and corroborated by lower breakdown voltages resulting from reductions in feature size. Low quiescent current in a battery-operated system is an intrinsic performance parameter because it partially determines battery life. This paper discusses some techniques that enable the practical realizations of low quiescent current LDO's at low voltages and in existing technologies. The proposed circuit exploits the frequency response dependence on load-current to minimize quiescent current flow. Moreover, the output current capabilities of MOS power transistors are enhanced and drop-out voltages are decreased for a given device size. Other applications, like dc-dc converters, can also reap the benefits of these enhanced MOS devices. An LDO prototype incorporating the aforementioned techniques was fabricated. The circuit was operable down to input voltages of 1 V with a zero-load quiescent current flow of 23 /spl mu/A. Moreover, the regulator provided 18 and 50 mA of output current at input voltages of 1 and 1.2 V, respectively.

A high-efficiency CMOS voltage doubler

Abstract: A charge pump cell is used to make a voltage doubler using improved serial switches. A complete power efficiency theory is presented which fits the measurements. The importance of capacitors is shown with plots of power efficiency versus load and stray capacitors. Several problems arising at low voltage or high frequency are developed and some optimizations are presented. The substrate current is totally suppressed by the technique of bulk commutation. A power efficiency of 95% has been reached using external capacitors. A fully integrated charge pump is also presented and shows a maximum power efficiency of 75%.

MOS charge pumps for low-voltage operation

Abstract: New MOS charge pumps utilizing the charge transfer switches (CTSs) to direct charge flow and generate boosted output voltage are described. Using the internal boosted voltage to backward control the CTS of a previous stage yields charge pumps that are suitable for low-voltage operation. Applying dynamic control to the CTSs can eliminate the reverse charge sharing phenomenon and further improve the voltage pumping gain. The limitation imposed by the diode-configured output stage can be mitigated by pumping it with a clock of enhanced voltage amplitude. Using the new circuit techniques, a 1.2-V-to-3.5-V charge pump and a 2-V-to-16-V charge pump are demonstrated.

A 10-b, 500-MSample/s CMOS DAC in 0.6 mm/sup 2/

Abstract: A 10-b current steering CMOS digital-to-analog converter (DAC) is described, with optimized performance for frequency domain applications. For sampling frequencies up to 200 MSample/s, the spurious free dynamic range (SFDR) is better than 60 dB for signals from DC to Nyquist. For sampling frequencies up to 400 MSample/s, the SFDR is better than 55 dB for signals from DC to Nyquist. The measured differential nonlinearity and integral nonlinearity are 0.1 least significant bit (LSB) and 0.2 LSB, respectively. The circuit is fabricated in a 0.35-/spl mu/m, single-poly, four-metal, 3.3 V, standard digital CMOS process and occupies 0.6 mm/sup 2/. When operating at 500 MSample/s, it dissipates 125 mW from a 3.3 V power supply. This DAC is optimized for embedded applications with large amounts of digital circuitry.

A 12-bit intrinsic accuracy high-speed CMOS DAC

Abstract: A 12-bit intrinsic accuracy digital-to-analog (D/A) converter integrated in a standard digital 0.5 /spl mu/m CMOS technology is presented. It is based on a current steering doubly segmented 6+2+4 architecture and requires no calibration, no trimming, or dynamic averaging. The differential nonlinearity (DNL) and integral nonlinearity (INL) are 0.3 and 0.6 least significant bits (LSB's), respectively. The measured glitch energy is 1.9 pV.s. For a 12-bit resolution, the converter reaches an update rate of 300 MS/s. By reducing the voltage supply of the latches to 2.0 V, the glitch energy is reduced to sub-pV.s, and the update rate reaches 500 MS/s, for a resolution of 8 bits. The worst case power consumption is 320 mW, and it operates from a single 3.3 V voltage supply. The die area is 3.2 mm/sup 2/.

A digital background calibration technique for time-interleaved analog-to-digital converters

Abstract: A 10-bit 40-Msample/s two-channel parallel pipelined ADC with monolithic digital background calibration has been designed and fabricated in a 1 /spl mu/m CMOS technology. Adaptive signal processing and extra resolution in each channel are used to carry out digital background calibration. Test results show that the ADC achieves a signal-to-noise-and-distortion ratio of 55 dB for a 0.8-MHz sinusoidal input, a peak integral nonlinearity of 0.34 LSB, and a peak differential nonlinearity of 0.14 LSB, both at a 10-bit level. The active area is 42 mm/sup 2/, and the power dissipation is 565 mW from a 5 V supply.

High-performance microprocessor design

Abstract: Three generations of Alpha microprocessors have been designed using a proven custom design methodology. The performance of these microprocessors was optimized by focusing on high-frequency design. The Alpha instruction set architecture facilitates high clock speed, and the chip organization for each generation was carefully chosen to meet critical paths. Digital has developed six generations of CMOS technology optimized for high-frequency design. Complex circuit styles were used extensively to meet aggressive cycle time goals. CAD tools were developed internally to support these designs. This paper discusses some of the technologies that have enabled Alpha microprocessors to achieve high performance.

An MOS transistor model for analog circuit design

Abstract: This paper presents a physically based model for the metal-oxide-semiconductor (MOS) transistor suitable for analysis and design of analog integrated circuits. Static and dynamic characteristics of the MOS field-effect transistor are accurately described by single-piece functions of two saturation currents in all regions of operation. Simple expressions for the transconductance-to-current ratio, the drain-to-source saturation voltage, and the cutoff frequency in terms of the inversion level are given. The design of a common-source amplifier illustrates the application of the proposed model.

Variable supply-voltage scheme for low-power high-speed CMOS digital design

Abstract: This paper describes a variable supply-voltage (VS) scheme. From an external supply, the VS scheme automatically generates minimum internal supply voltages by feedback control of a buck converter, a speed detector, and a timing controller so that they meet the demand on its operation frequency. A 32-b RISC core processor is developed in a 0.4-/spl mu/m CMOS technology which optimally controls the internal supple voltages with the VS scheme and the threshold voltages through substrate bias control. Performance in MIPS/W is improved by a factor of more than two compared with its conventional CMOS design.

The impact of scaling down to deep submicron on CMOS RF circuits

Abstract: Recent papers reporting CMOS RF building blocks have aroused great expectations for RF receivers using deep-submicron technologies. This paper examines the trend in CMOS scaling, in order to establish the required current levels and achievable performance for different feature sizes, if robust, easily manufacturable designs are to be implemented for cellular applications. The boundary conditions (system-level constraints) for such designs, in terms of the number of trimmed and untrimmed external components and the roles they play in relaxing active circuit requirements, are emphasized throughout to make comparison of active RF circuits meaningful. At 1 GHz, 0.25-/spl mu/m CMOS appears to be the threshold for robust, low-NF RF front ends with current consumption competitive with today's BJT implementations.

A reduced clock-swing flip-flop (RCSFF) for 63% power reduction

Abstract: A reduced clock-swing flip-flop (RCSFF) is proposed, which is composed of a reduced swing clock driver and a special flip-flop which embodies the leakage current cutoff mechanism. The RCSFF can reduce the clock system power of a VLSI down to one-third compared to the conventional flip-flop. This power improvement is achieved through the reduced clock swing down to 1 V. The area and the delay of the RCSFF can also be reduced by a factor of about 20% compared to the conventional flip-flop. The RCSFF can also reduce the RC delay of a long RC interconnect to one-half.

Integrated circuit technology options for RFICs-present status and future directions

Abstract: This paper will summarize the technology tradeoffs that are involved in the implementation of radio frequency integrated circuits for wireless communications. Radio transceiver circuits have a very broad range of requirements-including noise figure, linearity, gain, phase noise, and power dissipation. The advantages and disadvantages of each of the competing technologies-Si CMOS and bipolar junction transistors (BJTs), Si/SiGe HBTs and GaAs MESFETs, PHEMTS and HBTs will be examined in light of these requirements.

A single-chip 900-MHz spread-spectrum wireless transceiver in 1-/spl mu/m CMOS. I. Architecture and transmitter design

Abstract: A single-chip transceiver for frequency-hopped code division multiple access (CDMA) in the 900 MHz industrial, scientific and medical (ISM) band is implemented in 1-/spl mu/m CMOS. It combines a digital frequency synthesizer, a double quadrature upconverter, an integrated oscillator, and a power amplifier with variable output. Data modulates a carrier hopping at 20 kHz with quaternary frequency-shift keying (4-FSK). At an output power level of +3 dBm, the harmonics and spurious tones lie at -52 dBc or below. When active, the transmitter drains 100 mA from 3 V.

Automated low-power technique exploiting multiple supply voltages applied to a media processor

Abstract: This paper describes an automated design technique to reduce power by making use of two supply voltages. The technique consists of structure synthesis, placement, and routing. The structure synthesizer clusters the gates off the critical paths so as to supply the reduced voltage to save power. The placement and routing tool assigns either the reduced voltage or the unreduced one to each row so as to minimize the area overhead. The reduced supply, voltage is also exploited in a clock tree to reduce power. Combining these techniques together, we applied it to a media processor chip. The combined technique reduced the power by 47% in random-logic modules and by 73% in the clock tree, while keeping the performance.

The multi-tanh principle: a tutorial overview

Abstract: This paper reviews a class of linear transconductance cells, having proven value in a variety of communications applications, characterized by the use of parallel- or series-connected sets of differential pairs of bipolar transistors whose inputs and outputs are connected in parallel. These cells invoke a well-developed concept, known as the "multi-tanh principle". The key idea is that the individually nonlinear (hyperbolic tangent, or tanh) transconductance functions may be separated along the input-voltage axis to achieve a much more linear overall function. The simplest of these is the so-called the "doublet"; the linearity criterion and noise behavior are discussed in detail. Some novel forms are presented. Higher order cells, including the "triplet", are then discussed, together with a novel method for achieving linear-in-dB gain control with an important modification for extending the dynamic range.

Compact low-voltage power-efficient operational amplifier cells for VLSI

Abstract: Compact low-voltage power-efficient operational amplifiers are described that are very suitable as very-large-scale-integration library cells because of the small die area of 0.08 mm/sup 2/ and the minimum supply voltage of 1.8 V. A key part of the circuit is the rail-to-rail class-AB output stage with folded mesh feedback control that combines power efficiency with operation down to 1.8 V and allows sufficient gain in a compact two-stage topology. A version with rail-to-rail input stage features a rail-to-rail input range for supply voltages down to 2.5 V. The dc gain of the op amps is more than 80 db while driving 10 k/spl Omega/, and the unity-gain frequency is 4 MHz with phase margin of 67/spl deg/ while driving 5 pF. The equivalent input noise voltage is 38 nV//spl radic/(Hz) at a frequency of 100 kHz. The amplifiers have been implemented in a standard digital 1.6-/spl mu/m complementary metal-oxide-semiconductor process.

A wireless implantable multichannel digital neural recording system for a micromachined sieve electrode

Abstract: This paper reports the development of an implantable, fully integrated, multichannel peripheral neural recording system, which is powered and controlled using an RF telemetry link. The system allows recording of /spl plusmn/500 /spl mu/V neural signals from axons regenerated through a micromachined silicon sieve electrode. These signals are amplified using on-chip 100 Hz to 3.1 kHz bandlimited amplifiers, multiplexed, and digitized with a low-power (<2 mW), moderate speed (8 /spl mu/s/b) current-mode 8-b analog-to-digital converter (ADC). The digitized signal is transmitted to the outside world using a passive RF telemetry link. The circuit is implemented using a bipolar CMOS process. The signal processing CMOS circuitry dissipates only 10 mW of power from a 5-V supply while operating at 2 MHz and consumes 4/spl times/4 mm/sup 2/ of area. The overall circuit including the RF interface circuitry contains over 5000 transistors, dissipates 90 mW of power, and consumes 4/spl times/6 mm/sup 2/ of area.

A replica technique for wordline and sense control in low-power SRAM's

Abstract: With the migration toward low supply voltages in low-power SRAM designs, threshold and supply voltage fluctuations will begin to have larger impacts on the speed and power specifications of SRAM's. We present techniques based on replica circuits which minimize the effect of operating conditions' variability on the speed and power. Replica memory cells and bitlines are used to create a reference signal whose delay tracks that of the bitlines. This signal is used to generate the sense clock with minimal slack time and control wordline pulsewidths to limit bitline swings. We implemented the circuits for two variants of the technique, one using bitline capacitance ratioing in a 1.2-/spl mu/m 8-kbyte SRAM, and the other using cell current ratioing in a 0.35-/spl mu/m 2-kbyte SRAM. Both the RAM's were measured to operate over a wide range of supply voltages, with the latter dissipating 3.6 mW at 150 MHz at 1 V and 5.2 /spl mu/W at 980 kHz at 0.4 V.

A 900-mV low-power /spl Delta//spl Sigma/ A/D converter with 77-dB dynamic range

Abstract: The design of a low-voltage and low-power /spl Delta//spl Sigma/ analog-to-digital (A/D) converter is presented. A third-order single-loop /spl Delta//spl Sigma/ modulator topology is implemented with the differential modified switched op-amp technique. The modulator topology has been transformed as to accommodate half-delay integrators. Dedicated low-voltage circuit building blocks, such as a class AB operational transconductance amplifier, a common-mode feedback amplifier, and a comparator are treated, as well as low-voltage design techniques. The influence of very low supply voltage on power consumption is discussed. Measurement results of the 900-mV /spl Delta//spl Sigma/ A/D converter show a 77-dB dynamic range in a 16-kHz bandwidth and a 62-dB peak signal-to-noise ratio for a 40-/spl mu/W power consumption.

High-frequency nonlinearity analysis of common-emitter and differential-pair transconductance stages

Abstract: Equations describing the high-frequency nonlinear behavior of common-emitter and differential-pair transconductance stages are derived. The equations show that transconductance stages using inductive degeneration are more linear than those using capacitive or resistive degeneration, and that the common-emitter transconductance stages are more linear than the differential-pair transconductance stages with the same bias current and transconductance. The nonlinearity equations can also be used to explain the class AB behavior of the common-emitter transconductance stage with inductive degeneration.

A monolithic 4-bit 2-Gsps resonant tunneling analog-to-digital converter

Abstract: The combination of resonant-tunneling diodes and heterostructure field-effect transistors provides a versatile technology for implementing microwave digital and mixed-signal applications. Here we demonstrate and characterize the first monolithic flash analog-to-digital converter (ADC) in this technology. The first-pass ADC achieved 2.7 effective bits at 2 gigasamples per second (Gsps) for a 220-MHz input signal. The one-bit quantizer achieved a single-tone spurious free dynamic range greater than 40 dB at 2 Gsps for a 220-MHz single-tone input with dithering.

A multipage cell architecture for high-speed programming multilevel NAND flash memories

Abstract: To realize low-cost, highly reliable, high-speed programming, and high-density multilevel flash memories, a multipage cell architecture has been proposed. This architecture enables both precise control of the V/sub th/ of a memory cell and fast programming without any area penalty. In the case of a four-level cell, a high programming speed of 236 /spl mu/s/512 bytes or 2.2 Mbytes/s can be obtained, which is 2.3 times faster than the conventional method. A small die size can be achieved with the newly developed compact four-level column latch circuit. A preferential page select method has also been proposed so as to improve the data retention characteristics. The IC error rate can be decreased by as much as 33%, and a highly reliable operation can be realized.

A 0.5-mW passive telemetry IC for biomedical applications

Abstract: A low-power, single-chip, one-channel, fully implantable microtransponder system for low-frequency biomedical sensor applications is described. The circuit is powered by an external RF source at 27/40 MHz. No battery is required. Wireless communication with external monitoring units is realized by absorption modulation. As the radiated power received by a small coil can be as low as a few milliwatts, the data acquisition/transmission system has been optimized for low power consumption. The system has been integrated in a 2-/spl mu/m 40-V BiCMOS technology. It includes a low-offset amplifier, a low-pass notch filter, an A/D converter, a voltage doubler/rectifier, as well as a low-power voltage regulator. The implemented switched-capacitor amplifier features 45-/spl mu/V offset and an integrated noise of 21 /spl mu/V for a bandwidth of 30 Hz while consuming less than 30 /spl mu/W power. The digitized sensor data are transmitted as low duty-cycle PPM-AM signals with a rate of 1 kBd. The entire system, including the 1.6-k/spl Omega/ bridge sensor, consumes only 520 /spl mu/W, which makes it well suited for long-term monitoring of biomedical signals.

A 1.1-V current-mode and piecewise-linear curvature-corrected bandgap reference

Abstract: A low-voltage, micropower, curvature-corrected bandgap reference is presented that is capable of working down to input voltages of 1.1 V in a relatively inexpensive process, MOSIS 2 /spl mu/m technology. This is a vanilla N-well complementary metal-oxide-semiconductor process technology with an added P-base layer. Second-order curvature correction for this reference is accomplished by a versatile piecewise-linear current-mode technique. The 0.595 V precision reference achieved a line regulation performance of 408 ppm/V for input voltages between 1.2 and 10 V. The circuit only used 14 /spl mu/A of quiescent current flow.

A high-swing CMOS telescopic operational amplifier

Abstract: A high-swing, high-performance CMOS telescopic operational amplifier is described. The high swing of the op-amp is achieved by employing the tail and current source transistors in the deep linear region. The resulting degradation in differential gain, common-mode rejection ratio (CMRR), and other amplifier characteristics are compensated by applying regulated-cascode differential gain enhancement and a replica-tail feedback technique. A prototype of the op-amp has been built in a 0.81-/spl mu/m CMOS process. Operating from a power supply of 3.3 V, it achieves a differential swing of /spl plusmn/2.15 V, a differential gain of 90 dB, unity-gain frequency of 90 MHz, and >50-dB CMRR. It is shown, analytically and through simulations, that the operational amplifier maintains its high CMRR even at high frequencies.

Monolithic transformers and their application in a differential CMOS RF low-noise amplifier

Abstract: A 900 MHz low-noise amplifier (LNA) utilizing three monolithic transformers to implement on-chip tuning networks and requiring no external components has been integrated in 2.88 mm/sup 2/ in a standard digital 0.6 /spl mu/m CMOS process. A bias current reuse technique is employed to reduce power dissipation, and process-, voltage-, and temperature-tracking biasing techniques are used. At 900 MHz, the LNA dissipates 18 mW from a single 3 V power supply and provides 4.1 dB noise figure, 12.3 dB power gain, -33.0 dB reverse isolation, and an input 1-db compression level of -16 dBm. Analysis and modeling considerations for silicon-based monolithic transformers are presented, and it is shown that a monolithic transformer occupies less die area and provides a higher quality factor than two independent inductors with the same effective inductance in differential applications.