This paper presents an analysis of the speed and power dissipation of various GaAs FET inverter circuits as prototypes of integrated logic circuit design. The analysis provides analytical expressions to assess the switching performance of enhancement-mode and depletion-mode MESFET's and JFET's with respect to switching-speed and power-dissipation capabilities in optimized configurations. Various load elements are described and analyzed for circuit applications. The various logic gates, now under development, are compared in their switching performance and a review of the state of the art is given. Prospects of large-scale integration (LSI) of gigabit logic for GaAs FET's are assessed.

Analysis of GaAs FET's for integrated logic

The development of a complete complementary MESFET technology is presented. The state-of-the-art, fully implanted, CMOS-like process uses Shannon implants together with a refractory silicide Schottky-gate material to combine high gate barrier heights with ease of fabrication. To minimize parasitic resistances, a unique sidewall structure and sidewall spacers are utilized to allow for self-aligned implantation of the source/drain regions. A self-aligned titanium silicidation technique is employed to minimize sheet and contact resistance of the source/drain regions. The SUPREM process simulator was employed extensively. The performance and modeling of device parameters (e.g., threshold voltage, gate leakage, and short-channel effects) and circuit parameters (e.g. standby current, noise margin, and speed) were accomplished through analytic formulations, the PISCES two-dimensional device simulator, and the SPICE circuit simulator. >

Device physics and technology of complementary silicon MESFET's for VLSI applications

A model for silicon Schottky barrier field-effect transistors (Si MESFETs) with micron and submicron dimensions has been implemented in the integrated circuit simulation program SPICE2. A description of the model and its implementation is given, together with a discussion of the physical effects that are important in submicron channel length Si MESFETs. The model is compared with d.c. experimental data with an emphasis on temperature dependence.

A MESFET model for circuit analysis

An ion-implanted silicon MESFET is scaled to smaller sizes assuming constant field within the device. Ion implantation is a leading techn.ology for VLSI and scaling is an important tool for device miniaturization. A one-dimensional and fairly accurate analysis is carried out considering the effect of side walls in the space-charge region below the gate in the below pinch-off region. Different device parameters such as drain-source current, threshold voltage, time delay, frequency, d.c. power dissipation and switching energy are plotted and discussed with respect to scaling factor for α. The results show how the ion-implanted silicon MESFET device can be optimized with the ad of scaling factor for better device performance.

On the scaling of an ion-implanted silicon MESFET

Complementary Si MESFETs (CMES) for integrated circuits using silicon-on-sapphire are described. Not only the gate, but also the source and drain of the n-transistors and p-transistors are Schottky junctions, using very high barrier heights for the gate and low barrier heights for source and drain. Only two Schottky metals are used: one, Ir or Pt, giving a high barrier on nSi, and hence low on pSi; the other, Er or Tb, showing the opposite behavior. The basic differences between MES and MOS are pointed out and design criteria for CMES inverters using normally-off type transistors are given. >

Complementary Si MESFET concept using silicon-on-sapphire technology

As an approach to an advanced LSI logic, a high-speed and low-power femto-joule logic circuit has been developed by using an enhancement-type Schottky barrier gate FET (ESBT) with31P implanted channel layer. A direct coupled transistor logic (DCTL) was designed using ESBT and resistor as a basic logic circuit. To evaluate the dynamic performance of the logic circuit, a 15-stage ring oscillator with an output buffer was integrated on a chip. A power-delay product was found in the femto-joule range. The logic swing is about 0.4 V and typical noise margin is 30 percent of the logic swing. A high-speed (40 ns) and low-power (10 mW) 4 bit ALU has been developed by using DCTL, NOR gates. Furthermore, improving ESBT channel layer carrier profile to the higher carrier concentration and abruptly changing shallower carrier profile by31P and11B double implantation resulted in advanced characteristics of ESBT and logic circuit using it as follows. ESBT transconductance was increased by a factor of two. Power-delay product reduced to 80 percent of that of logic circuit, using ESBT with31P single implanted channel layer, was satisfactorily confirmed, together with a circuit density as large as 300 gates/ mm2.

N. Kawamura

Papers

Femto Joule logic circuit with enhancement-type Schottky barrier gate FET

Logic Circuits with 2μm Gate Schottky Barrier FETs