Strained-silicon (Si) is incorporated into a leading edge 90-nm logic technology . Strained-Si increases saturated n-type and p-type metal-oxide-semiconductor field-effect transistors (MOSFETs) drive currents by 10 and 25%, respectively. The process flow consists of selective epitaxial Si/sub 1-x/Ge/sub x/ in the source/drain regions to create longitudinal uniaxial compressive strain in the p-type MOSFET. A tensile Si nitride-capping layer is used to introduce tensile uniaxial strain into the n-type MOSFET and enhance electron mobility. Unlike past strained-Si work: 1) the amount of strain for the n-type and p-type MOSFET can be controlled independently on the same wafer and 2) the hole mobility enhancement in this letter is present at large vertical electric fields, thus, making this flow useful for nanoscale transistors in advanced logic technologies.

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A logic nanotechnology featuring strained-silicon

A process is described for manufacturing an improved PMOS semiconductor transistor. Recesses are etched into a layer of epitaxial silicon. Source and drain films are deposited in the recesses. The source and drain films are made of an alloy of silicon and germanium. The alloy is epitaxially deposited on the layer of silicon. The alloy thus has a lattice having the same structure as the structure of the lattice of the layer of silicon. However, due to the inclusion of the germanium, the lattice of the alloy has a larger spacing than the spacing of the lattice of the layer of silicon. The larger spacing creates a stress in a channel of the transistor between the source and drain films. The stress increases IDSAT and IDLIN of the transistor. An NMOS transistor can be manufactured in a similar manner by including carbon instead of germanium, thereby creating a tensile stress.

Semiconductor transistor having a stressed channel

Semiconductor structures and devices including strained material layers having impurity-free zones, and methods for fabricating same. Certain regions of the strained material layers are kept free of impurities that can interdiffuse from adjacent portions of the semiconductor. When impurities are present in certain regions of the strained material layers, there is degradation in device performance. By employing semiconductor structures and devices (e.g., field effect transistors or “FETs”) that have the features described, or are fabricated in accordance with the steps described, device operation is enhanced.

Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same

Semiconductor-on-insulator structures facilitate the fabrication of devices, including MOSFETs that are at least partially depleted during operation and FinFETs including bilayer fins and/or crystalline oxide.

Hybrid fin field-effect transistor structures and related methods

Semiconductor industry has increasingly resorted to strain as a means of realizing the required node-to-node transistor performance improvements. Straining silicon fundamentally changes the mechanical, electrical (band structure and mobility), and chemical (diffusion and activation) properties. As silicon is strained and subjected to high-temperature thermal processing, it undergoes mechanical deformations that create defects, which may significantly limit yield. Engineers have to manipulate these properties of silicon to balance the performance gains against defect generation. This paper will elucidate the current understanding and ongoing published efforts on all these critical properties in bulk strained silicon. The manifestation of these properties in CMOS transistor performance and designs that successfully harness strain is reviewed in the last section. Current manufacturable strained-silicon technologies are reviewed with particular emphasis on scalability. A detailed case study on recessed silicon germanium transistors illustrates the application of the fundamentals to optimal transistor design.

Fundamentals of silicon material properties for successful exploitation of strain engineering in modern CMOS manufacturing

Future CMOS technology nodes bring new challenges to formation of source/drain junctions and their contacts to limit their series resistance contribution to ten percent of the device channel resistance. This requires not only extremely low junction sheet resistance values but also super abrupt doping profiles and contact resistivities that can not be obtained with the existing self-aligned silicide technology. In this paper, we present an overview of the SiGe junction technology designed to meet the demands of the future technology nodes down to 30 nm. The technology is based upon selective deposition of boron or phosphorus doped SiGe in source/drain areas isotropically etched to the desired junction depth. The technology is limited to temperatures below 800/spl deg/C. Hence; it is also compatible with future high-/spl kappa/ gate stacks, which can not withstand higher temperatures. The results indicate that the technology offers great promise in meeting the demands of the end-of-the-roadmap devices.

Ultra-shallow source/drain junctions for nanoscale CMOS using selective silicon-germanium technology

Future CMOS technology nodes bring new challenges to formation of source/drain junctions and their contacts. To avoid MOSFET performance degradation with scaling, series resistance contribution of each junction must be limited to five percent of the device channel resistance. This requires ultra-shallow junctions with extremely low sheet, spreading and contact resistance. In this paper, we present an overview of the SiGe junction technology recently proposed by this laboratory for nanoscale CMOS. The technology is based on selective deposition of boron or phosphorus doped SiGe alloys in source/drain regions isotropically etched to the desired junction depth. Since the dopant atoms naturally occupy the substitutional sites during growth, the need for an activation anneal is completely eliminated limiting the maximum process temperature to 550°C for boron and 750°C for phosphorus. In this temperature range, dopant diffusion is virtually eliminated resulting in extremely abrupt doping profiles. Elimination of the high temperature implant anneal also makes the process compatible with the thermal stability needs of future high-K gate dielectrics. A key advantage of the technology is its potential to reduce the junction contact resistance. SiGe provides a smaller bandgap under the metal contact resulting in a smaller metal-semiconductor barrier height. Since the contact resistivity is an exponential function of the barrier height, the technology provides a significant advantage in reducing the contact resistivity. The results to date indicate that the technology is a promising alternative for nanoscale CMOS source/drain junctions and their contacts.

N. Pesovic

Papers

Ultra-shallow source/drain junctions for nanoscale CMOS using selective silicon-germanium technology

Selective Silicon-Germanium Source/Drain Technology for Nanoscale Cmos