Revisiting MOSFET threshold voltage extraction methods

In this work, we extend the “Y function” method to the saturation regime of MOSFET operation. This allowed us for the first time to extract a low charge apparent mobility up to high drain voltage and consequently the saturation velocity without the need of source drain series resistance correction. The method has successfully been applied to silicon (Si) and germanium (Ge) bulk technologies and the nonconvergence of linear mobility and saturation velocity improvement is highlighted.

“Y function” method applied to saturation regime: Apparent saturation mobility and saturation velocity extraction

An analytical drain-current compact model for lightly doped short-channel ultrathin-body and box fully depleted silicon-on-insulator MOSFETs with back-gate control is presented. The model includes the effects of drain-induced barrier lowering, channel-length modulation, saturation velocity, mobility degradation, quantum confinement, velocity overshoot, and self-heating. The proposed model has been validated by comparing with the experimental transfer and output characteristics of devices with the channel lengths of 30 and 240 nm and with back bias varying from −3 to +3 V. The good accuracy of the model makes it suitable for implementation in circuit simulation tools.

Analytical Compact Model for Lightly Doped Nanoscale Ultrathin-Body and Box SOI MOSFETs With Back-Gate Control

Threshold voltage (VTH) is the most evocative aspect of MOSFET operation. It is the crucial device constraint to model on-off transition characteristics. Precise VTH value of the device is extracted and evaluated by several estimation techniques. However, these assessed values of VTH diverge from the exact values due to various short channel effects (SCEs) and non-idealities present in the device. Numerous prevalent VTH extraction methods are discussed. All the results are verified by extensive 2-D TCAD simulation and confirmed through analytical results at 10-nm technology node. Aim of this research paper is to explore and present a comparative study of largely applied threshold extraction methods for bulk driven nano-MOSFETs especially at 10-nm technology node along with various sub 45-nm technology nodes. Application of the threshold extraction methods to implement noise analysis is briefly presented to infer the most appropriate extraction method at nanometer technology nodes.

https://file.scirp.org/pdf/CS_2016113013184132.pdf

Comparative Methodical Assessment of Established MOSFET Threshold Voltage Extraction Methods at 10-nm Technology Node

The feasibility of geometric magnetoresistance (MR) measurement from linear to saturation operation regime is demonstrated in ultrathin body and BOX fully depleted silicon-on-insulator devices from 14-nm technology node. Besides, we propose a new physical compact model for MOSFET drain current under high field transport, which reproduces experimental MR mobility from linear to saturation operation region and serves as the basis for a new extraction method of carrier saturation velocity. A benchmarking with state-of-the-art saturation velocity extraction methodologies is also conducted. Our saturation velocity results indicate that, for this technology, nonstationary transport prevails as manifested by an overshoot velocity behavior, still far from the ballistic limit.

Experimental and Theoretical Investigation of Magnetoresistance From Linear Regime to Saturation in 14-nm FD-SOI MOS Devices

This paper presents a new modified Y function method for parameter extraction of nano scale MOSFETs, taking into account the gate voltage dependent source-drain series resistance R SD in the linear operation regime. Two approaches have been considered. The first one explores Y function without any prior assumption on R SD (V g ) while the second one assumes a linear R SD (V g ) for simpler extraction. Both methods were applied to real devices and successfully extracted the parameters.

Parameter extraction of nano-scale MOSFETs using modified Y function method

The effect of magnetic field in the saturation regime of sub µm MOSFETs is being reported here for the first time. The study was based on bulk MOSFETs featuring a high-κ/metal gate with an equivalent oxide thickness of 2.4 nm. Channel length ranged from 1 µm down to 50 nm, while width was kept constant at 10 µm. It is found that it is possible to extract a magnetoresistance mobility µMR even in the saturation regime of operation and in turn study the observed µMR against channel length, temperature, drain voltage and gate voltage. For these sub-micron devices, electron transport is influenced by the high electric field that exists in the channel and velocity saturation, velocity overshoot and even quasi-ballistic effects could play a role for the shortest channel lengths Here, the observed µMR behavior is well interpreted using velocity saturation and overshoot effects.

http://ieeexplore.ieee.org/iel5/6341168/6359978/06360041.pdf

N. Subramanian

Papers

Parameter extraction of nano-scale MOSFETs using modified Y function method

Magnetoresistance mobility extraction in the saturation regime of short channel MOS devices