scispace - formally typeset
M

Mireille Mouis

Researcher at University of Grenoble

Publications -  142
Citations -  2273

Mireille Mouis is an academic researcher from University of Grenoble. The author has contributed to research in topics: Nanowire & Field-effect transistor. The author has an hindex of 22, co-authored 135 publications receiving 2012 citations. Previous affiliations of Mireille Mouis include Los Angeles Harbor College & University of Savoy.

Papers
More filters
Journal ArticleDOI

Ultrathin Nanogenerators as Self‐Powered/Active Skin Sensors for Tracking Eye Ball Motion

TL;DR: In this paper, the Ultrathin piezoelectric nanogenerator (NG) with a total thickness of ≈16 μm is fabricated as an active or self-powered sensor for monitoring local deformation on a human skin.
Journal ArticleDOI

Carrier transport in HfO/sub 2//metal gate MOSFETs: physical insight into critical parameters

TL;DR: In this article, the effect of remote coulomb scattering (RCS) due to fixed charges or dipoles on electron and hole mobility in HfO/sub 2/metal gate MOSFETs was studied through low-temperature measurements.
Journal ArticleDOI

Performance Optimization of Vertical Nanowire-based Piezoelectric Nanogenerators

TL;DR: In this article, the mechanical and electrical structures of the integrated nanogenerator as an integrated system are optimized, and strategies for concentrating the mechanical strain field in the vertical nanowire arrays and increasing the force sensitivity are developed.
Journal Article

Performance Optimization of Vertical Nanowire-Based Piezoelectric Nanogenerators

TL;DR: In this paper, the mechanical and electrical structures of the integrated nanogenerator as an integrated system are optimized, and strategies for concentrating the mechanical strain field in the vertical nanowire arrays and increasing the force sensitivity are developed.
Journal ArticleDOI

Revisited parameter extraction methodology for electrical characterization of junctionless transistors

TL;DR: In this paper, junctionless transistors (JLTs) fabricated on (100) silicon on insulator (SOI) wafer with 145mm and 9mm silicon thickness were considered.