Binary Neural Networks (BNNs) are rapidly gaining remarkable attention due to their superiority in shrinking the model size, which outstandingly mitigates the fundamental “memory wall” bottleneck that is attributed to the existing von-Neumann architectures. This work investigates how principles from approximate computing can be effectively employed to further optimize BNNs. It demonstrates that HW/SW codesign, in which BNNs are either proactively trained in the presence of approximation-induced errors (i.e. design-time optimization) and/or augmented with an appropriate error-mitigation scheme (i.e., run-time optimization), is a key to realize energy-efficient yet robust BNNs. We unveil, for the first time, that although the underlying HW of BNNs can be implemented using simple XNOR gates, the complexity of the required “Popcount” circuit super-linearly grows with the filter kernel size. This largely impacts the area footprint, inference time, energy, and hence it severely constricts the prospective efficiency gains from BNNs. To overcome this challenge, we replace the accurate full adders constructing the Popcount with Majority gates that approximately perform the required additions. Then, our carefully-crafted error-mitigation scheme along with activations tuning considerably minimizes the induced errors. Afterward, abstracted error probabilities are derived and employed during BNN training to obtain approximation-aware BNNs, that are inherently robust against the underlying HW approximation. Differently from the typical approaches, the proposed HW/SW codesign methodology has the merit of allowing a training of the approximate BNN without the need to modify the existing software frameworks (i.e., PyTorch). This is of great importance since existing tools rely on efficient built-in functions that can be difficult and/or inefficient to be modified. An FPGA-based SoC realizing both accurate and approximation-aware BNNs is developed for validating our proposed methodology. With merely a 4.7% loss in the inference accuracy, our HW/SW codesign leads to 64% and 80.2% savings in the area and energy, respectively, at the parity of the latency. Our results are obtained using commercial EDA tool flows employing a commercial 28nm FDSOI technology node.

HW/SW Codesign for Approximation-Aware Binary Neural Networks

As the artificial intelligence and Internet of Things (AIoT) develop rapidly, the deployment of artificial neural networks in edge computing is becoming significant with great challenge. The binarized convolutional neural network (BCNN) is one of the most widely adopted light-weight ANNs in AIoT, which can achieve the balance of system accuracy and hardware resource consumption, compared to others. To achieve high power and area efficiency in BCNN deployment, many approximate computing (AxC) techniques are integrated to make full use of the resilience of BCNN. As the research focused on the integration of AxC in circuit design, the design of AxC itself is not fully considered when applied to specific applications or domains. Based on circuit-architecture-system co-design, this article proposes an efficient BCNN deployment method, including a quality-circuit co-design method for approximate adder generation, a quality-aware intercompensation approach for addition tree, and a computing quality involved retraining approach for BCNN deployment. Experimental results show that the proposed quality model can achieve 86.43% in average accuracy while evaluating nine types of typical approximate adders. The proposed method is conducted on the applications of keyword spotting of GSCD, MNIST, and CIFAR-10, and we can further rise the approximation degree by 50%–75%, while reducing the accuracy by less than 1%.

An Efficient BCNN Deployment Method Using Quality-Aware Approximate Computing

Among various energy improvement techniques, approximate computing can reduce power, area and delay at the cost of calculation accuracy losses. In this paper, we propose an approximate signed multiplier design with a low power consumption and a short critical path using Cartesian Genetic Programming (CGP) algorithm and a compressors evolution method to obtain more suitable approximate 3-2 compressors for partial products (PPs) accumulation to compensate the error generated by CGP. Experimental results show that the proposed signed multiplier reduces delay by 42%, area by 25%, power consumption by 24% and the power delay product (PDP) by 56.6%. The NMED of proposed multiplier and recognition accuracy increased from 0.885% to 0.736% and 87.29% to 92.61% respectively through compressors evolution method. The proposed multiplier is also evaluated in a CRNN-based keyword spotting (KWS) system which brought high efficiency and little accuracy loss.

Compressors Evolution based High Speed and Energy Efficient Approximate Signed Multiplier

Approximate computing (AC) is an innovative paradigm for error-resilient signal processing applications. Addition is often a fundamental function for many of these applications. Particularly, binarized weight network (BWN) eliminates the multiplication by quantizing the weight to 1 bit, and the convolution can be achieved by simple accumulation. To further improve the energy efficiency of BWN, an approximate computing architecture based on the reconfigurable approximate adder with dual-VDD is proposed. The precision of the proposed approximate addition structure can be configured by setting approximate bit-width (ABW), and different voltage supplies can be configured for the approximate adder to reduce power consumption. A keywords-spotting (KWS) processor based on an optimized BWN is then used as a case study of the proposed approximate computing architecture. Implemented and evaluated under 22nm technology, the power consumption of the proposed BWN accelerator can be reduced by 54.3%, while the accuracy loss is only 0.4%.

Na Xie

Papers

An Efficient BCNN Deployment Method Using Quality-Aware Approximate Computing

Compressors Evolution based High Speed and Energy Efficient Approximate Signed Multiplier

A Reconfigurable Approximate Computing Architecture With Dual-VDD for Low-Power Binarized Weight Network Deployment