Various exemplary embodiments of the present disclosure relate to an apparatus and method for outputting content in an electronic device. In this case, the electronic device includes a display module, a power module configured to interrupt power supply to at least one element of the electronic device based on a control signal, and a processor. The processor may be configured to transmit to the power module the control signal for interrupting the power supply to the processor if a designated condition is satisfied, and transmit content information to the display module so that the display module displays the content information when the power supply to the processor is interrupted.

Method for displaying content and electronic device thereof

A communications device, a communications system, a method, and a computer readable storage device having a non-transitory computer program stored thereon, are disclosed. All of these are directed to reducing power consumption associated with processing of audio-video (AV) content, such as streaming video.

Power saving audio-video playback

One embodiment of the present invention sets forth a method for displaying images. The method includes causing a graphics processing unit (GPU) to transmit first display data to a variable refresh rate display at a first refresh rate. The method also includes detecting a level of idleness associated with the display data. The method also includes causing the GPU to enter a low-power state based at least in part on the level of idleness and causing the GPU to exit the low-power state. Finally, the method includes causing the GPU to transmit second display data to the variable refresh rate display to refresh an image displayed on the variable refresh rate display.

Low-power state with a variable refresh rate display

Scalable transform architectures and their implementation for graphic accelerators and communication

Disclosed herein are techniques to coordinate power management between a platform and a panel. Provided are apparatuses, techniques, and circuitry to determine whether to initiate power management features in a panel and send a signal from a platform to the panel including an indication that no frame updates are expected and power management functions can be initiated.

Co-existence of full frame and partial frame idle image updates

Technologies for low-power display refresh standby include a computing device with a display such as an LCD panel. The computing device may include a system-on-a-chip (SoC) with a processor, I/O subsystem, display controller, and memory. When the computing device determines that a display image is static, the computing device enters a low-power display refresh standby mode, powering down unneeded components of the SoC such as processor cores, peripheral devices, and memory other than a dedicated display buffer. The display controller may access the dedicated display buffer via the I/O subsystem and output the image to the display. The computing device may power down the I/O subsystem and the dedicated display buffer when a display controller FIFO is full of image data, and periodically power on the I/O subsystem and display buffer to fill the display controller FIFO. Other embodiments are described and claimed.

Technologies for low-power standby display refresh

In this paper we present a hardware architecture suitable for implementing discrete trigonometric transforms (DTT) including popular fast Discrete Cosine (DCT) and Sine (DST) transforms. The design method is modular and uses predesigned components to construct a transform system. A data shuffle network structure is presented in this work and we will show how it is used in conjunction with a partial column structure to build and compute the transforms. The scalability is based only on the transform size and the number of processing elements (PE). The transform throughput is determined by the number of PE and its associated shuffle network size. In this work we use a scalable DCT-II algorithm with a constant geometry structure to present the design methodology. The design approach can be applied to implement other discrete trigonometric transforms with similar property.

Design method for scalable discrete trigonometric transforms (DTT) with constant geometry

The number of processing elements (PE) can be reduces significantly using partial column structure to perform Discrete Trigonometric Transform (DTT) computation. Data reordering is required between stages (columns). A scalable interconnect network for both global and local for data reordering is presented in this paper. The network scalability is based on the transform size and the number of processing elements (PE). The structure will reorder data on the fly and eliminate the need of memory. This will help evaluating throughput vs. complexity (cost and area.). Detail analysis of hardware cost will be presented

Implementation of scalable interconnect networks for data reordering used in Discrete Trigonometric Transforms (DTT)

Adaptive computing systems (ACSs) are flexible hardware accelerators for applications in domains such as image and digital signal processing. However, the mapping of applications onto ACSs using the traditional methods can take long time for a hardware engineer to develop and debug. A software design environment called CHAMPION was developed at the University of Tennessee to enable the automated mapping of applications onto ACSs. In this paper the compilation path of CHAMPION is described and a new recursive partitioning method based on topological ordering and levelization (RPL) is presented. The proposed method performs multi-FPGA partitioning by taking into account six different partitioning constraints.

Netlist partitioning method suitable for adaptive computing systems

Scalable architectures were proposed for Discrete Cosine Transform (DCT). Number of processing elements (PE) can be reduced significantly using partial column structure for computing the DCT transform. This feature is very desirable for multimedia applications usage in handheld devices. As per transform computation, data reordering is required between stages (columns) where intermediate computed values are saved in memory-like temporary locations called FIFO's. A scalable interconnect network for both global and local data reordering and its implementation is presented in this paper. Scalability is based on transform size and desired number of processing elements (PE). The structure gives choice flexibility of throughput vs. complexity (cost and area.) of the overall system.

Nabil Kerkiz

Papers

Technologies for low-power standby display refresh

Design method for scalable discrete trigonometric transforms (DTT) with constant geometry

Implementation of scalable interconnect networks for data reordering used in Discrete Trigonometric Transforms (DTT)

Netlist partitioning method suitable for adaptive computing systems

Scalable interconnect networks for Discrete Cosine Transforms (DCT) for mobile and multimedia application