In recent years lattice-based cryptography has emerged as quantum secure and theoretically elegant alternative to classical cryptographic schemes (like ECC or RSA). In addition to that, lattices are a versatile tool and play an important role in the development of efficient fully or somewhat homomorphic encryption (SHE/FHE) schemes. In practice, ideal lattices defined in the polynomial ring ℤp[x]/〈xn+1〉 allow the reduction of the generally very large key sizes of lattice constructions. Another advantage of ideal lattices is that polynomial multiplication is a basic operation that has, in theory, only quasi-linear time complexity of ${\mathcal O}(n \log{n})$ in ℤp[x]/〈xn+1〉. However, few is known about the practical performance of the FFT in this specific application domain and whether it is really an alternative. In this work we make a first step towards efficient FFT-based arithmetic for lattice-based cryptography and show that the FFT can be implemented efficiently on reconfigurable hardware. We give instantiations of recently proposed parameter sets for homomorphic and public-key encryption. In a generic setting we are able to multiply polynomials with up to 4096 coefficients and a 17-bit prime in less than 0.5 milliseconds. For a parameter set of a SHE scheme (n=1024,p=1061093377) our implementation performs 9063 polynomial multiplications per second on a mid-range Spartan-6.

Towards efficient arithmetic for lattice-based cryptography on reconfigurable hardware

In this paper, we describe a processor architecture tailored for radix-4 and mixed-radix FFT algorithms, which have lower arithmetic complexity than radix-2 algorithms. The processor is based on transport triggered architecture and several optimizations have been used to improve the energy-efficiency. The processor has been synthesized on a 130nm standard cell technology and analysis show that a programmable solution can possess energy-efficiency comparable to a fixed-function ASIC.

Low-power application-specific processor for FFT computations

In this paper, a processor architecture tailored for radix-4 and mixed-radix FFT computations is described. The processor has native support for power-of-two transform sizes. Several optimizations have been used to improve the energy-efficiency of the processor and experiments show that a programmable solution can possess energy-efficiency comparable to fixed-function ASICs.

Low-Power Application-Specific Processor for FFT Computations

A number of recent works have considered the problem of constructing constant-time hash functions to various families of elliptic curves over finite fields. In the relevant literature, it has been occasionally asserted that constant-time hashing to certain special elliptic curves, in particular so-called BN elliptic curves, was an open problem. It turns out, however, that a suitably general encoding function was constructed by Shallue and van de Woestijne back in 2006. In this paper, we show that, by specializing the construction of Shallue and van de Woestijne to BN curves, one obtains an encoding function that can be implemented rather efficiently and securely, that reaches about 9/16ths of all points on the curve, and that is well-distributed in the sense of Farashahi et al., so that one can easily build from it a hash function that is indifferentiable from a random oracle.

Progress in Cryptology – LATINCRYPT 2012

This paper demonstrates the FPGA implementation of FFT algorithm that is precisely designed to induce an efficient implementation of the parameters involving area and performance by configuring the size of FFT input points which is well suited for wireless and signal processing applications. An optimized architecture is demonstrated in this paper for computing FFT of length 8/16/32/64/128/512 and 1024 using Radix-4/Radix 2∗2 FFT in FPGA and is compared with Xilinx LogiCore™ FFT IP with configurable point size. It is found that proposed design is more efficient and effective in terms of area and performance while achieving the input system configurability. A novel Address Generator architecture has been proposed which facilitates for Complex Math Processor (CMP). This single generator helps in effectively carrying out the address mapping scheme. The occurrence of hardware overheads is minimized by using the multiplexor for complex arithmetic's. The entire RTL design is described using Verilog HDL and simulated using Xilinx ISim. This experimental result is tested on Spartan-6 XC6SLX4, which is the smallest device on Spartan 6 family and found that Xilinx FFT IP core over maps the available DSP48 slices. The result shows 538 LUT's, 847 Flip Flops, 3 DSP Slices, Maximum Frequency of 217 MHz. This is about 60% improvement in resource usage and 14% upgrade in the performance thus creating a low cost Configurable FFT Processor.

Efficient hardware implementation of scalable FFT using configurable Radix-4/2

The paper presents a family of architectures for FFT implementation based on the decomposition of the perfect shuffle permutation, which can be designed with variable number of processing elements. This provides designers with a trade-off choice of speed vs. complexity (cost and area.). A detailed case study is provided on the implementation of 1024-point FFT with 2 processing elements using 45 nm process technology, including area, timing, power and place-and-route results.

/pdf/a-family-of-scalable-fft-architectures-and-an-implementation-145lp1pepy.pdf

A family of scalable FFT architectures and an implementation of 1024-point radix-2 FFT for real-time communications

This paper presents a family of architectures for FFT implementation based on the decomposition of the perfect shuffle permutation, which can be designed with variable number of processing elements. This provides designers with a trade-off choice of speed vs. complexity (cost and area.). Hardware comparison to other existing pipeline architecture presented based on implementation of 1024-point FFT with 4 processing elements using 45nm process technology. The proposed architecture is most suitable for handheld and portable multimedia applications

Scalable FFT architecture vs. multiple pipeline FFT architectures — Hardware implementation and cost

In this paper we present a hardware architecture suitable for implementing discrete trigonometric transforms (DTT) including popular fast Discrete Cosine (DCT) and Sine (DST) transforms. The design method is modular and uses predesigned components to construct a transform system. A data shuffle network structure is presented in this work and we will show how it is used in conjunction with a partial column structure to build and compute the transforms. The scalability is based only on the transform size and the number of processing elements (PE). The transform throughput is determined by the number of PE and its associated shuffle network size. In this work we use a scalable DCT-II algorithm with a constant geometry structure to present the design methodology. The design approach can be applied to implement other discrete trigonometric transforms with similar property.

Design method for scalable discrete trigonometric transforms (DTT) with constant geometry

The number of processing elements (PE) can be reduces significantly using partial column structure to perform Discrete Trigonometric Transform (DTT) computation. Data reordering is required between stages (columns). A scalable interconnect network for both global and local for data reordering is presented in this paper. The network scalability is based on the transform size and the number of processing elements (PE). The structure will reorder data on the fly and eliminate the need of memory. This will help evaluating throughput vs. complexity (cost and area.). Detail analysis of hardware cost will be presented

Implementation of scalable interconnect networks for data reordering used in Discrete Trigonometric Transforms (DTT)

Scalable architectures were proposed for Discrete Cosine Transform (DCT). Number of processing elements (PE) can be reduced significantly using partial column structure for computing the DCT transform. This feature is very desirable for multimedia applications usage in handheld devices. As per transform computation, data reordering is required between stages (columns) where intermediate computed values are saved in memory-like temporary locations called FIFO's. A scalable interconnect network for both global and local data reordering and its implementation is presented in this paper. Scalability is based on transform size and desired number of processing elements (PE). The structure gives choice flexibility of throughput vs. complexity (cost and area.) of the overall system.

Adel Hussein

Papers

A family of scalable FFT architectures and an implementation of 1024-point radix-2 FFT for real-time communications

Scalable FFT architecture vs. multiple pipeline FFT architectures — Hardware implementation and cost

Design method for scalable discrete trigonometric transforms (DTT) with constant geometry

Implementation of scalable interconnect networks for data reordering used in Discrete Trigonometric Transforms (DTT)

Scalable interconnect networks for Discrete Cosine Transforms (DCT) for mobile and multimedia application