An all-pass filter architecture that can be generalized to high orders, and can be realized using active circuits is proposed. Using this, a compact true-time-delay element with a widely tunable delay and a large delay-bandwidth product (DBW) is demonstrated. This is useful for beamforming and equalization in the lower GHz range where the use of $LC$ or transmission line-based solutions to realize large delays is infeasible. Coarse tuning of delay is realized by changing the filter’s order while keeping the bandwidth constant and fine tuning is implemented by changing the filter’s bandwidth utilizing the delay-bandwidth tradeoff. A test chip fabricated in 0.13 $\mu \text{m}$ CMOS process demonstrates a delay tuning range of 250 ps–1.7-ns, over a bandwidth of 2 GHz, while maintaining a magnitude deviation of ±0.7 dB. The filter achieves a DBW of 3.4 and a delay per unit area of 5.8 $\mathrm {ns/mm^{2}}$ . The filter has a worst case noise figure of 23 dB, and −40 dB intermodulation (IM3) distortion for 37 mVppd inputs. The chip occupies an active area of 0.6 mm2, and dissipates 112 mW–364 mW of power between its minimum and maximum delay settings. Computed radiation pattern with four antennas spaced $\mathrm {\lambda _{fmax}}/2$ apart shows ±90° beam steering off broadside.

A 2-GHz Bandwidth, 0.25–1.7 ns True-Time-Delay Element Using a Variable-Order All-Pass Filter Architecture in 0.13 $\mu$ m CMOS

Advanced Ultrawideband Radar : Signals, Targets, and Applications

This paper presents the design of the first CMOS distributed active power combiners and splitters with wideband variable delay and gain. These circuits are the key components for use in multi-antenna (MA) ultra-wideband (UWB) point-to-point beamforming communication systems with multiple transmit and receive antennas. Two broadband circuit topologies for each active power combiner and splitter are proposed, one of which being fabricated in a 0.13-μm CMOS process. The proposed fabricated distributed active power combiner and splitter operate across wide range of frequencies that cover the UWB frequency range from 3.1 to 10.6 GHz. The gain of each RF path of the power combiner and splitter is independently controllable from -15 to 6 dB and from -16 to 9.5 dB, respectively. The wideband variable delay of each RF path varies from 32 to 42 ps for the two-stage power combiner, and from 43 to 53 ps for the three-stage power splitter across the UWB frequency rang. Supplied from 1.8-V DC voltage, the power combiner and splitter consume 8.5 mA and 11.4 mA, respectively.

CMOS distributed active power combiners and splitters for multi-antenna UWB beamforming transceivers

This paper presents a true time delay (TTD)-based transmit/receive (T /R) chipset with 508 ps time delay and 31.5 dB amplitude control for large-scale wideband timed array. The proposed T /R chipset consists of a true time delay circuit, a switched T -type attenuator, and digital control circuits. To compensate the frequency dependent insertion loss characteristics of single-pole double-throw switches, artificial transmission line (ATL), passive-based attenuator, and wideband bi-directional active double-pole double-throw (DPDT) switches are included in the design. In addition, low-path filters (LPFs) with T -type attenuators are applied to the reference signal path to minimize amplitude variations during time delay control. The proposed T /R chipset demonstrates a record delay-range bandwidth product and a flat in-band characteristic of −3.6 dB with ±3.6 dB variation in both operations (transmit and receive) over 2–20 GHz.

A True Time Delay-based SiGe Bi-directional T/R Chipset for Large-Scale Wideband Timed Array Antennas

We introduce a ladder filter-based programmable time-delay element for beamforming in ultra-wideband (UWB) systems. Such a lumped-element realization becomes possible by approximating e
 -std
 as a ratio of polynomials (based on Taylor and Pade expansions). When compared with conventional methods based on the tapped delay-line architecture, the proposed technique achieves lower power dissipation, higher delay range and resolution, and better area efficiency. A prototype delay line designed for the 3.1-10.6 GHz UWB range achieves a delay range of 140 ps and a gain range of -30 dB to +10 dB. Fabricated in a 0.25 μm SiGe BiCMOS process, the delay element occupies an active area of 1 mm
 2
 and consumes 53 mW from a 2.5 V supply. A four-antenna beamforming system using the delay element can achieve a scanning range of ±61
 °
 with 0.86 °
 resolution for an antenna spacing of 15 mm.

Design of Lumped-Component Programmable Delay Elements for Ultra-Wideband Beamforming

UWB pulse waveforms based on modified Hermite polynomials are spectrally efficient and mutually orthogonal. A reconfigurable generation of these UWB signals is a challenge. In this work, we present a programmable pulse shaping filter based on singly-terminated LC ladders. By appropriate setting of the filter taps, a variety of shapes related to a Gaussian pulse can be generated. Experimental results from a test chip designed in a 0.25 μm BiCMOS process are given.

Programmable analog pulse shaping for ultra-wideband applications

We introduce a ladder filter based programmable time delay element for beamforming in Ultra-Wideband (UWB) systems When compared to conventional methods based on the tapped delay line architecture, our technique achieves lower power dissipation, better area efficiency, and finer delay and gain resolution more efficiently The proposed architecture is more scalable, has better parasitic absorption capability and highly programmable with delay and gain resolution dependent only on transconductor resolution A prototype delay line designed for the 31-106 GHz UWB range achieves a delay range of 80 ps with 05 ps resolution and a gain range of -30 dB to +10 dB with 015 dB step Fabricated in a 025 μm SiGe BiCMOS process, the delay element occupies an active area of 1 mm2 and consumes 47 mW from a 25 V supply A four antenna beamforming system using the delay element can achieve scanning range of ± 51° with resolution of 086 ° for antenna spacing of 10 mm

A lumped component programmable delay element for Ultra-Wideband beamforming

Accurate characterization of fully differential on-chip filters and amplifiers whose bandwidths extend to several GHz is challenging. Measurement using a packaged chip is convenient, but not accurate due to nonidealities of the package. In this work, we demonstrate that the use of on-chip polarity reversal buffers greatly enhances accuracy by reducing the effect of finite package isolation and by mitigating errors due to common-mode to differential mode conversion. Further, the technique also allows differential characterization using only two-port single-ended measurements, without compromising much on accuracy. Measurements on an integrated 7 GHz Bessel filter made using this technique show good consistency up to 20 GHz whether the chip is probed or bench characterized after mounting in a QFN package.

http://ieeexplore.ieee.org/iel7/7155722/7166703/07166912.pdf

Naga Rajesh

Papers

Design of Lumped-Component Programmable Delay Elements for Ultra-Wideband Beamforming

Programmable analog pulse shaping for ultra-wideband applications

A lumped component programmable delay element for Ultra-Wideband beamforming

Improved characterization of differential multi-Ghz integrated amplifiers and filters