An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

A process for removing at least a portion of a film from a substrate, such as a wafer of silicon or other similar materials, the film on the substrate typically being an oxide film, maintaining the atmosphere embracing the substrate at near room temperature and at near normal atmospheric pressure, flowing dry inert diluent gas over the substrate, introducing a flow of reactive gas, preferably an anhydrous hydrogen halide gas, namely anhydrous hydrogen flouride gas, for typically 5 to 30 seconds over the substrate and film to cause the removal of portions of the film, flowing water vapor laden inert gas, preferably nitrogen, over the substrate and film from a time prior to commencing flow of the reactive gas until flow of the reactive gas is terminated. In the case of non-hygroscopic film on the substrate, the flow of water vapor continues during the flow of the reactive gas and is terminated shortly after the termination of the flow of reactive gas. In the case of hygroscopic film, the flow of water vapor is discontinued prior to the start of flow of the reactive gas. In carrying out the process, a process chamber is needed to confine the substrate and have a vent, which though restricted, continuously open to the atmosphere.

Gaseous process and apparatus for removing films from substrates

This invention clarifies the effects of parameters and enables the mass production of a super-junction semiconductor device, which has a drift layer composed of a parallel pn layer that conducts electricity in the ON state and is depleted in the OFF state. The quantity of impurities in n drift regions is within the range between 100% and 150% or between 110% and 150% of the quantity of impurities in p partition regions. The impurity density of either one of the n drift regions and the p partition regions is within the range between 92% and 108% of the impurity density of the other regions. In addition, the width of either one of the n drift regions and the p partition regions is within the range between 94% and 106% of the width of the other regions.

Semiconductor device with alternating conductivity type layer and method of manufacturing the same

Disclosed is an improved Reactive Ion Etch (RIE) technique for etching polysilicon or single crystal silicon as must be done in Very Large Scale Integration (VLSI) using silicon technology. It teaches the use of an etch gas that consists of a mixture of sulfur hexafluoride (SF 6 ) and chlorine (Cl 2 ) diluted with inert gas. This etch gas allows an RIE process which combines the very desirable features of selectivity (high Si/SiO 2 etch rate ratio) and directionality which creates vertical side walls on the etched features. Vertical side walls mean no mask undercutting, hence zero etch bias. It is particularly applicable to device processing in which micron or sub-micron sized lines must be fabricated to extremely close tolerances. It is a distinct improvement over wet chemical etching or plasma etching as it is conventionally applied.

Selective reactive ion etching of polysilicon against SiO2 utilizing SF6 -Cl2 -inert gas etchant

A charge coupled device is fabricated from a monocrystalline semiconductor-on-insulator (SOI) composite structure.

SOI methods and apparatus

The lateral transistor is described which has both its base width and the emitter region of the transistor minimized. This minimization of the elements of the lateral transistor gives high performance. The lateral transistor which may be typically PNP transistor is formed in a monocrystalline semiconductor body having a buried N+ region within the body. A P type emitter region is located in the body. An N type base region is located around the side periphery of the emitter region. A P type collector region is located in the body surrounding the periphery of the base region. A first P+ polycrystalline silicon layer acting as an emitter contact for the emitter region is in physical and electrical contact with the emitter region and acts as its electrical contact. A second P+ polycrystalline silicon layer is located on the surface of the body to make physical and electrical contact with the collector region. A vertical insulator layer on the edge of the second polycrystalline silicon layer isolates the two polycrystalline silicon layers from one another. The N base region at its surface is located underneath the width of the vertical insulator layer. An N+ reach-through region extending from the surface of the body to the buried N+ region acts as an electrical contact through the N+ region layer to the base region. The width of the vertical insulator has a width which is equal to the desired base width of the lateral PNP transistor plus lateral diffusions of the collector and emitter junctions of the lateral PNP. The preferred structure is to have the emitter formed around the periphery of a channel or groove which has at its base an insulating layer such as silicon dioxide. The parasitic transistor is almost totally eliminated by this buried oxide isolation.

Fabrication methods for high performance lateral bipolar transistors

A method for manufacturing a high performance bipolar device and the resulting structure which has a very small emitter-base spacing is described. The small emitter-base spacing, reduces the base resistance compared to earlier device spacing and thereby improves the performance of the bipolar device. The method involves providing a silicon semiconductor body having regions of monocrystalline silicon isolated from one another by isolation regions and a buried subcollector therein. A base region is formed in the isolated monocrystalline silicon. A mask is formed on the surface of the silicon body covering those regions designated to be the emitter and collector reach-through regions. A doped polycrystalline silicon layer is then formed through the mask covering the base region and making ohmic contact thereto. An insulating layer is formed over the polysilicon layer. The mask is removed from those regions designated to be the emitter and collector reach-through regions. The emitter junction is then formed in the base region and the collector reach-through formed to contact the buried subcollector. Electrical contacts are made to the emitter and collector. The doped polycrystalline silicon layer is the electrical contact to the base regions.

High performance bipolar device and method for making same

A method for making a high performance bipolar transistor characterized by self-aligned emitter and base regions and minimized base and emitter contact spacing. The disclosed method comprises forming a recessed oxide-isolated structure having opposite conductivity epitaxial layer and substrate. Multiple layered mass of alternating silicon nitride and silicon dioxide layers are placed over the base region and over the collector reach-through region. Polycrystalline silicon is deposited between the mesas. The mesas are undercut-etched to expose the extrinsic base region which is ion implanted. Then, the mesas are removed to expose the emitter and intrinsic base regions as well as the collector reach-through regions. The latter exposed regions are ion implanted appropriately. Contacts are made directly to the emitter and collector reach-through regions and indirectly via the polysilicon to the base region.

Self aligned method for making bipolar transistor having minimum base to emitter contact spacing

A method for making lateral PNP or NPN devices in isolated monocrystalline silicon pockets wherein silicon dioxide isolation surrounds the pocket and partially, below the surface, within the isolated monocrystalline region The P emitter or N emitter diffusion is made over the portion of the silicon dioxide that partially extends into the monocrystalline isolated pocket This structure reduces the vertical current injection which will give relatively high (beta) gain even at low base to emitter voltages The lateral PNP or NPN device resulting from the method is in a monocrystalline silicon pocket wherein silicon dioxide isolation surrounds the pocket and partially, below the surface, within the isolated monocrystalline silicon region The P emitter or N emitter diffusion is located over the portion of the silicon dioxide that partially extends into the monocrystalline isolated pocket

Method for making a lateral PNP or NPN with a high gain utilizing reactive ion etching of buried high conductivity regions

A method for making a filamentary pedestal transistor is disclosed in which epitaxial silicon is formed selectively above portions of a subcollector through the use of laser radiation. A single crystal substrate, having a subcollector of higher impurity concentration, is covered by an oxide mask which is apertured at two locations above the subcollector. Polycrystalline silicon is deposited over the apertured oxide mask. The structure is exposed to laser radiation of suitable energy level and wavelength to selectively convert the polycrystalline silicon to epitaxial monocrystalline silicon within and above the oxide apertures. The transistor is completed by conventional techniques to form base, emitter and collector reach-through regions.

Narasipur Gundappa Anantha

Papers

Fabrication methods for high performance lateral bipolar transistors

High performance bipolar device and method for making same

Self aligned method for making bipolar transistor having minimum base to emitter contact spacing

Method for making a lateral PNP or NPN with a high gain utilizing reactive ion etching of buried high conductivity regions

Selective epitaxy method using laser annealing for making filamentary transistors