An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

Evidence suggests that MOSFET degradation is due to interface-states generation by electrons having 3.7 eV and higher energies. This critical energy and the observed time dependence is explained with physical model involving the breaking of the ≡ Si s H bonds. The device lifetime τ is proportional to I_{sub}^{-2.9}I_{d}^{1.9}\Delta V_{t}^{1.5} . If I sub is large because of small L or large V d , etc., τ will be small. I sub (and possibly light emission) is thus a powerful predictor of τ. The proportionality constant has been found to vary by a factor of 100 for different technologies, offering hope for substantially better reliability through future improvements in dielectric /interface technologies. A simple physical model can relate the channel field E m to all the device parameters and bias voltages. Its use in interpreting and guiding hot-electron scaling are described. LDD structures can reduce E m and I sub and, when properly designed, reduce device degradation.

Hot-electron-induced MOSFET degradation&#8212;Model, monitor, and improvement

Evidence suggests that MOSFET degradation is due to interface-states generation by electrons having 3.7 eV and higher energies. This critical energy and the observed time dependence is explained with a physical model involving the breaking of the = Si/sub s/H bonds. The device lifetime /spl tau/ is proportional to...

Hot-Electron-Induced MOSFET Degradation - Model, Monitor, and Improvement

The process starts with a primary mask, which may be characterized as a pattern of parallel, photoresist strips having substantially vertical edges, each having a minimum feature width F, and being separated from neighboring strips by a minimum space width which is also approximately equal to F. From this primary mask, a set of expendable mandrel strips is created either directly or indirectly. The set of mandrel strips may be characterized as a pattern of parallel strips, each having a feature width of F/2, and with neighboring strips being spaced from one another by a space width equal to 3/2F. A conformal stringer layer is then deposited. The stringer layer material is selected such that it may be etched with a high degree of selectivity with regard to both the mandrel strips and an underlying layer which will ultimately be patterned using a resultant, reduced-pitch mask. The stringer layer is then anisotropically etched to the point where the top of each mandrel strip is exposed. The mandrel strips are then removed with an appropriate etch. A pattern of stringer strips remains which can then be used as a half-pitch mask to pattern the underlying layer. This process may also be repeated, starting with the half-pitch mask and creating a quarter-pitch mask, etc. As can be seen, this technique permits a reduction in the minimum pitch of the primary mask by a factor of 2-N (where N is an integer 1, 2, 3, . . . ).

Method for reducing, by a factor or 2-N, the minimum masking pitch of a photolithographic process

To prevent a point defect and a line defect in forming a light-emitting device, thereby improving the yield. A light-emitting element and a driver circuit of the light-emitting element, which are provided over different substrates, are electrically connected. That is, a light-emitting element and a driver circuit of the light-emitting element are formed over different substrates first, and then electrically connected. By providing a light-emitting element and a driver circuit of the light-emitting element over different substrates, the step of forming the light-emitting element and the step of forming the driver circuit of the light-emitting element can be performed separately. Therefore, degrees of freedom of each step can be increased, and the process can be flexibly changed. Further, steps (irregularities) on the surface for forming the light-emitting element can be reduced than in the conventional technique.

Light-emitting device and manufacturing method thereof

The LDD structure, where narrow, self-aligned n-regions are introduced between the channel and the n+source-drain diffusions of an IGFET to spread the high field at the drain pinchoff region and thus reduce the maximum field intensity, is analyzed. The design is shown, including optimization of the n-dimensions and concentrations and the boron channel doping profile and an evaluation of the effect of the series resistance of the n-regions on device transconductance. Characteristics of experimental devices are presented and compared to those of conventional IGFET's. It is shown that significant improvements in breakdown voltages, hot-electron effects, and short-channel threshold effects can be achieved allowing operation at higher voltage, e.g., 8.5 versus 5 V, with shorter source-drain spacings, e.g., 1.2 versus 1.5 µm. Alternatively, a shorter channel length could be used for a given supply voltage. Performance projections are shown which predict 1.7 × basic device/circuit speed enhancement over conventional structures. Due to the higher voltages and higher frequency operation, the higher performance results in an increase in power which must be considered in a practical design.

Design and characteristics of the lightly doped drain-source (LDD) insulated gate field-effect transistor

Methods for fabricating a semiconductor integrated circuit having a sub-micrometer gate length field effect transistor devices are described wherein a surface isolation pattern is formed in a semiconductor substrate which isolates regions of the semiconductor from one another. Certain of these semiconductor regions are designated to contain field effect transistor devices. An insulating layer which may be designated to be in part the gate dielectric layer of the field effect transistor devices is formed over the isolation pattern surface. Then a first polycrystalline silicon layer is formed thereover. A masking layer such as silicon dioxide, silicon nitride or the like is then formed upon the first polycrystalline layer. The structure is etched to result in a patterned first polycrystalline silicon layer having substantially vertical sidewalls some of which sidewalls extend across certain of the device regions. A controlled sub-micrometer thickness conductive layer is formed on these vertical sidewalls. The patterned layer is then removed which leaves the pattern of sub-micrometer thickness conductive sidewall layer portions of which extend across certain of the device regions. The sidewall conductive layer is utilized as the gate electrode of the field effect transistor devices. Ion implantation is then accomplished to form the desired source/drain element for the field effect devices in the device regions. The conductive layer and resulting gate electrode may be composed of polycrystalline silicon metal silicide or polycide (a combination of layers of polycrystalline silicon and metal silicide).

Fabrication process of sub-micrometer channel length MOSFETs

A fabrication process for the Lightly Doped Drain/Source Field-Effect Transistor, LDDFET, that utilizes RIE produced SiO 2 sidewall spacers is described. The process is compatible with most conventional polysilicon-gated FET processes and needs no additional photomasking steps. Excellent control and reproducibility of the n-region of the LDD device are obtained. Measurements from dynamic clock generators have shown that LDDFET's have as much as 1.9X performance advantage over conventional devices.

Fabrication of high-performance LDDFET's with Oxide sidewall-spacer technology

The LDD structure, where narrow, self-aligned n/sup -/ regions are introduced between the channel and the n/sup +/ source-drain diffusions of an IGFET to spread the high field at the drain pinchoff region and thus reduce the maximum field intensity, is analyzed. The design is shown, including optimization of then- dimensions and concentrations and the boron channel doping profile and an evaluation of the effect of the series resistance of the n- regions on device transconductance. Characteristics of experimental devices are presented and compared to those of conventional IGFET's. It is shown that significant improvements in breakdown voltages, hot-electron effects, and short-channel threshold effects can be achieved allowing operation at higher voltage, e.g., 8.5 versus 5 V, with shorter source-drain spacings, e.g., 1.2 versus 1.5 /spl mu/m. Alternatively, a shorter channel length could be used for a given supply voltage. Performance projections are shown which predict 1.7 X basic device/circuit speed enhancement over conventional structures. Due to the higher voltages and higher frequency operation, the higher performance results in an increase in power which must be considered in a practical design.

Design and Characteristics of the Lightly Doped Drain-Source (LDD) Insulated Gate Field-Effect Transistor

A method of manufacturing LDD MOS FET RAM capable of delineating short (less than 1 micrometer) lightly doped drain regions. An N- implant is effected between gate electrodes and field oxide insulators, before the N+ implant. An insulator layer is then deposited also prior to N+ ion implantation. Reactive ion etching of the layer leaves narrow dimensioned insulator regions adjacent the gate electrode which serves to protect portions of the N- impurity region during the subsequent N+ implant. These protected regions are the lightly doped source/drain regions.

Paul J. Tsang

Papers

Design and characteristics of the lightly doped drain-source (LDD) insulated gate field-effect transistor

Fabrication process of sub-micrometer channel length MOSFETs

Fabrication of high-performance LDDFET's with Oxide sidewall-spacer technology

Design and Characteristics of the Lightly Doped Drain-Source (LDD) Insulated Gate Field-Effect Transistor

Method of fabricating an MOS dynamic RAM with lightly doped drain