Showing papers by "Naresh R. Shanbhag published in 1995"

Pipelined adaptive DFE architectures using relaxed look-ahead

Abstract: Fine-grain pipelined adaptive decision-feedback equalizer (ADFE) architectures are developed using the relaxed look-ahead technique. This technique, which is an approximation to the conventional look-ahead computation, maintains functionality of the algorithm rather than the input-output behavior. Thus, it results in substantial hardware savings as compared to either parallel processing or look-ahead techniques. Pipelining of the decision feedback loop and the adaptation loop is achieved by the use of delay relaxation and sum relaxation. Both the conventional and the predictor form of ADFE have been pipelined. Results of the convergence analysis of the proposed algorithms are also provided. The performance of the pipelined algorithms for the equalization of a magnetic recording channel is studied. It is shown that the conventional ADFE results in an SNR loss of about 0.6 dB per unit increase in the speed-up factor. The predictor form of ADFE is much more robust and results in less than 0.1 dB SNR loss per unit increase in the speed-up factor. Speed-ups of up to 8 and 45 have been demonstrated for the conventional and predictor forms of ADFE. >

Pipelined adaptive IIR filter

Abstract: A pipelined adaptive infinite impulse response (PAIIR) filter is disclosed including an adaptive section and a non-adaptive section, where the PAIIR filter is responsive to first and second input signals. The PAIIR filter includes a plurality of delays and a first polynomial signal generator. The plurality of delays are adapted to re-time a first polynomial value signal, the second input signal, and an error signal. The first polynomial signal generator is adapted to perform relaxed look-ahead processing on the second input signal in the adaptive section. The first polynomial signal generator is responsive to the re-timed error signal so as to generate and adaptively update a first set of weight signals corresponding to first polynomial weights and so as to generate the first polynomial value signal therefrom.

Initial phase-loading circuit for a fractionally-spaced linear equalizer

Abstract: An initial phase-loading circuit (IPLC) for a fractionally-spaced linear equalizer (FSLE) includes a signal coupling component adapted to be coupled to the FSLE in a configuration so as to selectively introduce time-shifted discrete signals. The FSLE includes a set of initial filter tap coefficients that provide a discrete signal to the FSLE, perform discrete signal equalization using the FSLE at least until substantial convergence of the filter tap coefficients, and provide to the FSLE a time-shifted discrete signal to replace the previously provided discrete signal.

Pipelined adaptive IIR filter architecture

Abstract: The authors present fine-grain pipelined architectures for adaptive infinite impulse response (AIIR) filters. The AIIR filters are equation error based. The proposed architectures are developed by employing a combination of scattered look-ahead and relaxed look-ahead pipelining techniques. The scattered look-ahead technique is applied do the non-adaptive (but time-varying) recursive section. The relaxed look-ahead technique is applied to the adaptive blocks. It is shown via simulations that speed-ups of up to 8 and more can be achieved with marginal or no degradation in performance.