Digitally controlled oscillators are the main cores in all-digital phase-locked loops (ADPLL), which are important for determining the range of frequency and power consumption in ADPLLs. In the conventional digitally controlled oscillator (DCO) designs, one single band of operation is assigned to the DCO. The following paper presents a new approach in the design of DCOs, which works in dual-band and wide-band modes with a control unit. In dual-band mode, the DCO works in two different ranges of frequencies simultaneously via digital control bits. The wide-band DCO (WBDCO) works in one wider range of frequencies consecutively. It seems that in the wide-band DCO, the gap width for the dual-band DCO (DBDCO) is zero. The previously mentioned designs allow the designer to have standard frequencies with the help of direct or multiplied frequencies. So, we can have a trade-off between power and performance. This means that we can have low power consumption in low-frequency applications and vice versa. The proposed designs are based on using digitally controlled capacitors, current starving gates and Schmitt triggers in critical points of the DCO loop, while preserving coarse and fine tunings. The non-delay linearity factors are clearly investigated and resolved with the use of a new combined control unit. The simulations of the proposed designs are performed in Hspice with a voltage of $$\mathrm{VDD}=1.8$$VDD=1.8 v in 180 nm CMOS technology for 64- and 128-bit input coarse codes. Our simulation and evaluation results showed that in the dual-band DCO, a 14.8 ps jitter was calculated at 134 MHz with 1.2131 mW power consumption, while in the wide band with overlap mode, a 68.7 ps jitter was measured at 184.61 MHz with 1.604 mW power consumption. Our designs are proper for reconfigurable and multi-standard ADPLL designs.

Two Efficient Dual-Band and Wide-Band Low-Power DCO Designs Using Current Starving Gates, DCV and Reconfigurable Schmitt Triggers in 180 nm

L’Onera developpe des capteurs inertiels MEMS vibrants avec des performances qui peuvent interesser des applications spatiales. Les electroniques analogiques traditionnellement associees ne sont a priori pas limitantes par rapport aux performances physiques des capteurs. En revanche, elles se montrent encombrantes, non reconfigurables, et ne delivrent pas les grandeurs mesurees sous forme numerique a l’ordinateur de bord. En outre,dans le cadre d’une utilisation spatiale, elles sont sujettes a dependance et a obsolescence :le remplacement d’un composant implique une nouvelle qualification.Cette these propose une nouvelle architecture numerique generique, limitant au maximum les composants analogiques necessaires. Les travaux portent principalement sur deux capteurs developpes par l’Onera : l’accelerometre a lame vibrante VIA et le gyrometre vibrant a effet Coriolis VIG, mais sont justement transposables a d’autres familles. Une premiere fonction cle identifiee est la datation d’evenements pour la mesure de frequence et de phase, une seconde concerne la synthese numerique directe de frequence pour le pilotage de resonateurs, et une troisieme traite la generation de signaux sinusoidaux purs a partir des trains binaires delivres par le systeme numerique. Ces fonctions sont realisees sous forme de peripheriques numeriques autour d’un processeur embarque, le tout synthetise sur composant programmable FPGA. Le manuscrit debute par un rappel des lois physiques et des technologies de mesure inertielle, suivi d’une revue des oscillateurs, analogiques et numeriques, afin de determiner l’architecture numerique souhaitee. Le chapitre suivant aborde de facon theorique les fonctions numeriques envisagees, et en determine les elements de performance. La mise en oeuvre de ces fonctions et les premiers resultats experimentaux sont ensuite presentes d’abord au niveau de la fonction seule, et enfin dans une architecture complete incluant le capteur et le logiciel embarque, pour fournir de vraies mesures inertielles. Ces resultats encouragent le deploiement d’electronique numerique dans les prochaines generations de capteurs.

https://tel.archives-ouvertes.fr/tel-01809008/document

Microsystèmes inertiels vibrants pour applications spatiales : apport des fonctions numériques

The great advancement in CMOS technology, high speed and frequency, low jitter, low noise and phase noise, and less expensive phase-locked loop are very important in transceiver fields. This work aims at reviewing the performance of oscillators, phase and frequency detector (PFD), and charge pump (CP) for type-I PLL. In this work, the oscillators are reviewed as voltage-controlled oscillators (VCOs) and coherent-based phase-locked synchronous oscillator (CPSO). The phase and frequency detector is evolved as XOR gate PFD, double edge-triggered PFD, and digital pulse amplifier. The condition for stable operation and low-phase noise is established. The different types of oscillators and PFDs are reviewed. A detailed analysis of various methods to design oscillator, phase and frequency detector is provided. The best method to design phase and frequency detector is digital pulse amplifier. It minimizes the dead zone and phase error that can be easily recognized by flip-flop which is type D, and this amplifier has AND gates and is connected in series to raise the pulse width. The best method to design an efficient oscillator is the coherent phase-locked synchronous oscillator from various oscillators under study. It provides a method for improved frequency and lock-in range, capture range over the other oscillators. It retains the normal oscillator characteristics with less phase shifts across the frequency tuning and locking range.

A Preliminary Study of Oscillators, Phase and Frequency Detector, and Charge Pump for Phase-Locked Loop (PLL) Applications

In this paper, we present a very low jitter recon-figurable shunt capacitor delay line. The delay line produces configurable linear delay for pulse synchronization of high data rate coherent template based IR-UWB receivers. The delay line is composed of coarse and fine synchronization delay stages. The delay values of 52 pS/step, 17.5 pS/step and 4.5 pS/step and their combinations are possible with 32 control steps. 5 bit up/down counters with asynchronous reset are employed to achieve minimum pin number as well as fast configuration on the delay line. The maximum frequency of the input signal is 600 MHz. Incremental control steps can be configured in less than 1 nS. Long time additive jitter is measured as 2.3 pS.

A high resolution and low jitter linear delay line for IR-UWB template pulse synchronization

Using recently the developed dual band digitally controlled oscillator, in this paper, it can be proposed a low-power dual band all digital PLL (ADPLL). In the proposed ADPLL, toggling the input control bit utilizes the ADPLL to switch between two special frequency bands. An additional control circuit is also employed to have reasonable linearity. Sustaining coarse and fine characteristics and with a blend of capacitive shift and Schmitt trigger techniques, this oscillator changes the trigger points of the circuit and thus results in changeable delay and therefore, in creation of two different frequency bands. If the multiples of these bands used, it can cover two different frequency bands with one input toggling situation. It can be utilized in situation when it switched between two different frequencies for two unlike application or multi-standard bands. In such an occasion, instead of using two ADPLLs, the proposed structure, which decreases the needed area, can be used. Moreover, in this method, there is no need for redesigning and appraising the degree of stability against voltage changes, temperature and process of two ADPLLs. Simulation of the proposed dual band ADPLL is performed with Hspice by a voltage of VDD = 1.8v in 180 nm CMOS technology. The frequency range of the proposed dual band digitally controlled oscillator is from 97.18 to 117.65 MHz in lower band and 134.05---177.03 MHz in the high band.

A 14.8 ps jitter low-power dual band all digital PLL with reconfigurable DCO and time-interlined multiplexers

In this paper, an all digital phase locked loop is proposed. The proposed ADPLL uses counter for locking the output signal. The proposed circuit has a simple structure in locking mechanism, and the power consumption of this design is very low. The proposed design is evaluated in TSMC 180nm and PTM 32nm. The power consumption of the proposed ADPLL for 180nm, at 403 MHz frequency is 2.5mW and in 32nm at 720MHz is 1.33 mW. Two novel blocks are introduced for glitch removing in ADPLL and any other digital circuit. The reduction of glitches also affects on low power design. The digitally controlled oscillator (DCO) used here is based on ring oscillators with fine and coarse bits applied on it. The DCO achieves very high resolution with 0.1 ps due to 16-bit control code.

A new low-power and low-complexity all digital PLL (ADPLL) in 180nm and 32nm

In this paper, the bandwidth of the delta sigma modulator (DSM)-transmitter is improved using low complexity time-interleaved DSM The high clock speed requirement of DSM is the main limitation to increase the signal bandwidth in DSM-transmitter In this research, the bandwidth of DSM-transmitter is increased four times by using low complexity four-branch time-interleaved parallel DSM without the need for increasing clock speed This low complexity parallel DSM is designed based on polyphase implementation technique Then, the transmitter architecture is simulated using MATLAB simulink and Advanced Design System (ADS) For this simulation, the uplink long-term evolution (LTE) signal with different bandwidths of up to 768 MHz is used The simulation shows that by using four-branch time-interleaved parallel DSM in transmitter architecture for 768 MHz LTE signal with oversampling ratio (OSR) of 16, the signal to noise and distortion ratio (SNDR) is about 41 dB with the clock speed of only 3072 MHz This is four times lower than the required clock speed of the conventional transmitter to achieve the same SNDR

Bandwidth enhancement in delta sigma modulator transmitter using low complexity time-interleaved parallel delta sigma modulator

In this letter, a new all digital phase locked loop (ADPLL) is proposed. The proposed ADPLL is introduced a new locking procedure with low complexity which results in an ultra low power design. The design uses only two up-down counters for finding the reference frequency. An efficient glitch removal filter and a new low power DCO are also introduced in this letter. The DCO achieves a reasonably high resolution of 1ps. The power consumption of the proposed ADPLL at 500MHz frequency is 820µW. The proposed ADPLL is simulated in 180nm CMOS with Hspice and verified by MATLAB.

An ultra low power and low complexity all digital PLL with a high resolution digitally controlled oscillator

In this paper, an ultra low power 15-bit digitally controlled oscillator is proposed. The proposed DCO is designed based on a segmental coarse-tuning stage and employs hysteresis delay cell (HDC) and digitally controlled varactor (DCV) in the fine-tuning stage. The proposed circuit has a simple structure, and the power consumption of this design is very low. Simulation of proposed DCO using TSMC 180nm model achieves controllable frequency range of 205MHz ~ 925MHz with a wide linearity. Monte Carlo simulation demonstrates that the time-period jitter due to random power supply fluctuation is under 90 ps and the power consumption is 255µW at 205MHz with 1.8V power supply.

An ultra-low-power 15-bit digitally controlled oscillator with high resolution

In this paper, an ultra low power 15-bit digitally controlled oscillator (DCO) is proposed. The proposed DCO is designed based on a segmental coarse-tuning stage which employs novel Schmitt-trigger based hysteresis delay cells (HDC) as well as digitally controlled varactor (DCV) in the fine-tuning stage. Simulation of the proposed DCO using TSMC 180nm model achieves controllable frequency range of 191MHz ∼ 850MHz with a wide linearity. Monte Carlo simulation demonstrates that the time-period jitter due to random power supply fluctuation is under 124.8ps and the power consumption is 137µW at 215MHz with 1.8V power supply.

Nasser Erfani Majd

Papers

A new low-power and low-complexity all digital PLL (ADPLL) in 180nm and 32nm

Bandwidth enhancement in delta sigma modulator transmitter using low complexity time-interleaved parallel delta sigma modulator

An ultra low power and low complexity all digital PLL with a high resolution digitally controlled oscillator

An ultra-low-power 15-bit digitally controlled oscillator with high resolution

An ultra low-power digitally controlled oscillator using novel Schmitt-trigger based hysteresis delay cells