This paper presents a tutorial overview of ΣΔ modulators, their operating principles and architectures, circuit errors and models, design methods, and practical issues. A review of the state of the art on nanometer CMOS implementations is described, giving a survey of cutting-edge ΣΔ architectures, with emphasis on their application to the next generation of wireless telecom systems.

Sigma-Delta Modulators: Tutorial Overview, Design Guide, and State-of-the-Art Survey

The use of a VCO-based integrator and quantizer within a continuous-time (CT) ΔΣ analog-to-digital converter (ADC) structure is explored, and a custom prototype in a 0.13 μm CMOS with a measured performance of 81.2/78.1 dB SNR/SNDR over a 20 MHz bandwidth while consuming 87 mW from a 1.5 V supply and occupying an active area of 0.45 mm2 demonstrated. A key innovation is the explicit use of the oscillator's output phase to avoid the signal distortion that had severely limited the performance of earlier VCO-based ADCs, which had made use of its output frequency only. The proposed VCO-based integrator and quantizer structure enables fourth-order noise shaping with only three opamp-based integrators.

A 78 dB SNDR 87 mW 20 MHz Bandwidth Continuous-Time $\Delta\Sigma$ ADC With VCO-Based Integrator and Quantizer Implemented in 0.13 $\mu$ m CMOS

A method of monitoring an element in wireless communication system is provided. An operational noise measurement is obtained by measuring a noise value outside of a bandwidth of a first device, but within a bandwidth of a second, subsequent device. The operational noise measurement is alternatively obtained by tuning an input band of the element to shift the input band partially or completely outside of a bandwidth of a first device to create an open band or by suppressing an input of the antenna and measuring noise within the open bandwidth of the element of the wireless communication network. A stored parameter is retrieved and compared to the measured operational noise. Alternatively, a leakage signal of the element may be received at a signal receiver and compared to a reference. The reference is a function of components of the wireless communication system in a leakage path of the leakage signal.

Gain measurement and monitoring for wireless communication systems

A highly linear programmable-gain amplifier (PGA) is fabricated using a 0.35-/spl mu/m CMOS technology. High linearity and constant wide bandwidth are achieved by using a high-gain amplifier with low input impedance and resistor-network feedback. The voltage gain is varied by digitally controlling the input switched resistors. The distortion of a switched resistor has been analyzed using the Volterra series. The PGA has a voltage gain varying from 0 to 19 dB, while maintaining a constant bandwidth of 125 MHz. The third-order intermodulation distortion is -86dB at 10 MHz. The circuit dissipates 21 mW from a 3.3-V supply.

https://ir.nctu.edu.tw:443/bitstream/11536/27489/1/000185568500010.pdf

A highly linear 125-MHz CMOS switched-resistor programmable-gain amplifier

This paper presents a continuous-time (CT) ΔΣ modulator using a VCO-based internal quantizer. It incorporates a nonlinear VCO as the second stage in a two-stage residue canceling quantizer (RCQ) and mitigates the impact of its nonlinearity by spanning only a small region of the VCO's V-to-F nonlinear tuning curve. The order of noise shaping is increased by placing the RCQ in a continuous-time ΔΣ loop. Using only a first order loop filter, the proposed ΔΣ modulator achieves second order noise shaping. Fabricated in a 90-nm CMOS process, the prototype modulator occupies an active area of 0.36 mm2 and consumes 16 mW power. It achieves a peak SNDR of 78.3 dB in 10-MHz bandwidth and an SFDR of better than 85 dB when clocked at 600 MHz. The figure of merit of the modulator is 120 fJ/conv-step.

A 16-mW 78-dB SNDR 10-MHz BW CT $\Delta \Sigma$ ADC Using Residue-Cancelling VCO-Based Quantizer

This paper describes a continuous time DeltaSigma modulator with 10MHz of bandwidth that achieves a DR of 87dB and an IMD of -91dBc while consuming 100mW.

A 100mW 10MHz-BW CT ΔΣ Modulator with 87dB DR and 91dBc IMD

A quadrature bandpass DeltaSigma ADC for a multistandard TV tuner achieves a total dynamic range of 90 dB over an 8.5-MHz passband centered on 44 MHz while consuming 375 mW. The fourth-order continuous-time ADC uses active-RC resonators configured in a modified feedforward architecture

A 375-mW Quadrature Bandpass $\Delta\Sigma$ ADC With 8.5-MHz BW and 90-dB DR at 44 MHz

A quadrature bandpass ΔΣ ADC for a multistandard TV tuner achieves a total dynamic range of 90 dB over an 8.5-MHz passband centered on 44 MHz while consuming 375 mW. The fourth-order continuous-time ADC uses active-RC resonators configured in a modified feedforward architecture.

A 375-mW quadrature bandpass ΔΣ ADC with 8.5-MHz BW and 90-dB DR at 44 MHz

In one aspect, a calibration component configured to calibrate an automatic gain controller (AGC) for use in a tuner configured to isolate a selected channel from a multi-channel broadcast signal, the tuner implemented substantially on two chips, a first chip comprising a radio frequency (RF) integrated circuit adapted for RF processing and a second chip comprising a digital integrated circuit adapted for digital processing is provided. The calibration component comprises a calibration signal generator implemented on the RF integrated circuit, the calibration signal generator adapted to generate a generally known calibration signal, a power detector implemented on the RF integrated circuit and configured to detect, during calibration, at least one power characteristic of the calibration signal and to provide a power level signal indicative of the at least one detected power characteristic, a gain controller implemented on the digital integrated circuit, the gain controller adapted to generate at least one error signal based, at least in part, on a comparison between the power level signal provided by the power detector and a first reference signal, an offset signal generator implemented on the RF integrated circuit and configured to generate an offset signal based, at least in part, on the at least one error signal and a summing element implemented on the RF integrated circuit and adapted to combine the offset signal with the power level signal provided by the power detector to provide an adjusted power level signal.

Methods and apparatus for calibration of automatic gain control in broadcast tuners

A CT quadrature bandpass ADC is designed for a multi-standard television receiver. When clocked at 264MHz, the ADC achieves 90dB of total DR over an 8.5MHz BW centered at 44MHz. The 4th-order 4b ADC uses a modified feedforward topology and includes 12dB of AGC. The 2.5mm2 chip consumes 375mW in a 0.18mum CMOS process

Nazmy Abaskharoun

Papers

A 100mW 10MHz-BW CT ΔΣ Modulator with 87dB DR and 91dBc IMD

A 375-mW Quadrature Bandpass $\Delta\Sigma$ ADC With 8.5-MHz BW and 90-dB DR at 44 MHz

A 375-mW quadrature bandpass ΔΣ ADC with 8.5-MHz BW and 90-dB DR at 44 MHz

Methods and apparatus for calibration of automatic gain control in broadcast tuners

A 375mW Quadrature Bandpass /spl Delta//spl Sigma/ ADC with 90dB DR and 8.5MHz BW at 44MHz