This paper presents a tutorial overview of ΣΔ modulators, their operating principles and architectures, circuit errors and models, design methods, and practical issues. A review of the state of the art on nanometer CMOS implementations is described, giving a survey of cutting-edge ΣΔ architectures, with emphasis on their application to the next generation of wireless telecom systems.

Sigma-Delta Modulators: Tutorial Overview, Design Guide, and State-of-the-Art Survey

The use of a VCO-based integrator and quantizer within a continuous-time (CT) ΔΣ analog-to-digital converter (ADC) structure is explored, and a custom prototype in a 0.13 μm CMOS with a measured performance of 81.2/78.1 dB SNR/SNDR over a 20 MHz bandwidth while consuming 87 mW from a 1.5 V supply and occupying an active area of 0.45 mm2 demonstrated. A key innovation is the explicit use of the oscillator's output phase to avoid the signal distortion that had severely limited the performance of earlier VCO-based ADCs, which had made use of its output frequency only. The proposed VCO-based integrator and quantizer structure enables fourth-order noise shaping with only three opamp-based integrators.

A 78 dB SNDR 87 mW 20 MHz Bandwidth Continuous-Time $\Delta\Sigma$ ADC With VCO-Based Integrator and Quantizer Implemented in 0.13 $\mu$ m CMOS

At the turn of this century, there was widespread concern that the performance of analog-to-digital converters (ADCs) might have reached a saturation point and would, in fact, deteriorate as we began to scale into deep submicron CMOS technology. The past 15 years of innovation have clearly refuted such fears. Driven by a combination of application pull, architectural modifications, and relentless optimization, we have seen steady improvements in several key performance metrics.

The Race for the Extra Decibel: A Brief Review of Current ADC Performance Trajectories

A 14-bit SAR ADC is presented that achieves 73.6 dB SNDR at 80 MSPS while using a 1.2-V-only supply. In order to overcome throughput limitations common to conventional SAR ADCs, several techniques are proposed. First, a flash sub-ADC is utilized to resolve the 5 MSBs quickly prior to SAR sequential decisions of the LSBs. Second, the DAC operation is time-interleaved by a factor of 2, increasing speed while allowing a single comparator to be shared between all DACs. Third, fully on-chip DAC charge redistribution allows the DAC settling time to be improved by more than an order of magnitude compared to conventional techniques. Finally, the ADC is fully self-timed through the use of a replica timer circuit in order to take full advantage of the fast DAC settling and comparator decisions. Despite the increased speed, the ADC consumes only 31.1 mW and occupies a core area of 0.55 mm2.

A 14b 80 MS/s SAR ADC With 73.6 dB SNDR in 65 nm CMOS

A 12-bit 10-GS/s interleaved (IL) pipeline analog-to-digital converter (ADC) is described in this paper. The ADC achieves a signal to noise and distortion ratio (SNDR) of 55 dB and a spurious free dynamic range (SFDR) of 66 dB with a 4-GHz input signal, is fabricated in the 28-nm CMOS technology, and dissipates 2.9 W. Eight pipeline sub-ADCs are interleaved to achieve 10-GS/s sample rate, and mismatches between sub-ADCs are calibrated in the background. The pipeline sub-ADCs employ a variety of techniques to lower power, like avoiding a dedicated sample-and-hold amplifier (SHA-less), residue scaling, flash background calibration, dithering and inter-stage gain error background calibration. A push–pull input buffer optimized for high-frequency linearity drives the interleaved sub-ADCs to enable >7-GHz bandwidth. A fast turn-ON bootstrapped switch enables 100-ps sampling. The ADC also includes the ability to randomize the sub-ADC selection pattern to further reduce residual interleaving spurs.

A 12-b 10-GS/s Interleaved Pipeline ADC in 28-nm CMOS Technology

A sixth-order dc-to-1 GHz tunable continuous-time lowpass/bandpass ΔΣ ADC in 65-nm CMOS targeting RF and IF digitizing applications is presented. The ADC achieves 150-MHz bandwidth at 450-MHz center frequency with 74-dB dynamic range at 4-GHz sampling frequency while consuming 550 mW. This performance is enabled by a reconfigurable LC and active-RC modulator structure, fifth-order and seventh-order feedforward operational amplifiers, a self-cut-off comparator, and a dual-supply DAC.

A DC-to-1 GHz Tunable RF $\Delta \Sigma$ ADC Achieving DR $ =$ 74 dB and BW $ =$ 150 MHz at $f_{0} =$ 450 MHz Using 550 mW

This paper describes a continuous time DeltaSigma modulator with 10MHz of bandwidth that achieves a DR of 87dB and an IMD of -91dBc while consuming 100mW.

A 100mW 10MHz-BW CT ΔΣ Modulator with 87dB DR and 91dBc IMD

This paper presents a continuous-time (CT) multi-stage noise-shaping (MASH) ADC in 28 nm CMOS. The MASH ADC uses a first-order front-end stage to digitize the input signal and a second-order back-end stage to digitize the quantization noise of the coarse flash ADC inside the front-end. An RC lattice filter and a current-steering DAC are utilized to extract the front-end coarse quantization residue. The prototype MASH ADC chip built in a 28 nm CMOS process is clocked at 8 GHz with an OSR of 8.6, providing a signal bandwidth of 465 MHz. The ADC achieves a DR of 72 dB and an average small-signal NSD of −160 dBFS/Hz. The peak SNR is 68 dB and the peak SNDR is 67 dB. The IM3 is −88 dBFS with two −9 dBFS tones at the band edge. The ADC consumes 890 mW of power from +1.8/1.0/-1.0 V supplies and achieves a thermal noise FOM of 159 dB.

A 72 dB-DR 465 MHz-BW Continuous-Time 1-2 MASH ADC in 28 nm CMOS

The ultimate ADC for receiver applications would be one that converts any desired RF signal directly into digital form so that the rest of the signal chain enjoys accurate and flexible digital signal processing and CMOS scaling. Flexibility in center frequency (f 0 ), bandwidth (BW), sampling frequency (f S ), full-scale (FS), dynamic range (DR) and power consumption (P) would allow the ADC to handle multiple standards and adapt to the RF environment [1–4]. The ADC reported in this paper is a step toward this Holy Grail of ADCs, supporting f 0 = 0 to 1GHz, BW = 35 to 150MHz, f S = 2 to 4GHz and FS = −18dBm to +18dBm. At f 0 = 450MHz, BW = 150MHz, f S = 4GHz and FS = +6dBm, the ADC achieves instantaneous DR = 74dB and peak SNR = 69dB with P = 550mW.

A DC-to-1GHz tunable RF ΔΣ ADC achieving DR = 74dB and BW = 150MHz at f 0 = 450MHz using 550mW

A quadrature bandpass DeltaSigma ADC for a multistandard TV tuner achieves a total dynamic range of 90 dB over an 8.5-MHz passband centered on 44 MHz while consuming 375 mW. The fourth-order continuous-time ADC uses active-RC resonators configured in a modified feedforward architecture

Hajime Shibata

Papers

A DC-to-1 GHz Tunable RF $\Delta \Sigma$ ADC Achieving DR $ =$ 74 dB and BW $ =$ 150 MHz at $f_{0} =$ 450 MHz Using 550 mW

A 100mW 10MHz-BW CT ΔΣ Modulator with 87dB DR and 91dBc IMD

A 72 dB-DR 465 MHz-BW Continuous-Time 1-2 MASH ADC in 28 nm CMOS

A DC-to-1GHz tunable RF ΔΣ ADC achieving DR = 74dB and BW = 150MHz at f 0 = 450MHz using 550mW

A 375-mW Quadrature Bandpass $\Delta\Sigma$ ADC With 8.5-MHz BW and 90-dB DR at 44 MHz