Showing papers by "Neil Weste published in 1981"

Virtual Grid Symbolic Layout

Abstract: Free form or "stick" type symbolic layout provides a means of simplifying the design of IC subcircuits. To successfully utilize this style of layout, a complete design approach and the necessary tools to support this methodology are required. In particular, one of the requirements of such a design method is the ability to "compact" the loosely specified topology to create a set of valid mask data. This paper presents a new compaction strategy which uses the concept of a virtual grid. The compaction algorithm using the virtual grid is both simple and fast, an attribute which allows the designer to conveniently interact with the algorithm to optimize a layout. In addition to the compaction algorithm, methods used to create large building blocks will be described. The work described here is part of a complete symbolic layout system called MULGA which is written in the C programming language and resides on the UNIX operating system.

The edge flag algorithm — A fill method for raster scan displays

Abstract: Contour (polygon) filling is a primitive required in many application areas of raster scan graphics. The bit-map memory in a frame-store display is computationally well suited to this task, as it provides a large scratch pad working space. In this paper, a number of contour filling algorithms based on the read/write properties of the frame-store memory are compared with the classical `ordered-edge-list' approach. Performance is evaluated on a microcomputer controlled frame-store display system in terms of ability to fill correctly, execution speed and processor memory requirements. A new algorithm, based on a more exact definition of an object edge, is presented. This algorithm, denoted edge flag algorithm, is implemented within the frame-store memory. It features high speed, in conjunction with minimal CPU memory requirements, making it ideally suited to hardware or microcode (firmware) implementation.

Mulga — an interactive symbolic layout system for the design of integrated circuits

Abstract: To aid the design of MOS circuits, a suite of programs residing on the UNIX∗ operating system have been designed and written. These programs allow the interactive editing, layout compaction, circuit connectivity extraction, parasitic audit, and timing simulation of MOS ICs within the symbolic domain. The programs make use of an intermediate circuit description language (ICDL), which captures both geometric placement and circuit connectivity. A convenient interface is provided to enable the procedural definition of symbolic layouts in the C programming language. All design may be carried out at a single low-cost work station which incorporates a high-performance color display. In this paper we summarize the operation and use of these programs. In particular, we describe a new compaction algorithm.

Time warp signal recognition processor for matching signal patterns

Abstract: Known signal processors for matching signal patterns commonly compare an unknown signal with one of a set of reference signals Various comparison techniques are known One comparison technique for solving a parenthesization problem includes an orthogonal array of interconnected cells which are adapted for dynamic programming and for extending data and control information in a generally left-to-right direction as well as in a bottom-to-top direction For solving a pattern matching problem, known arrangements for extending control information in a generally left-to-right or bottom-to-top direction do not appear to be satisfactory The disclosed signal processor for matching signal patterns and for dynamically time warping an unknown input signal with a reference input signal generates a measure of the correspondence between the input signals In generating the correspondence measure, the processor includes an arrangement for controlling all processor cells on a predetermined diagonal of the array of cells Thereby all cells coupled to the diagonal can operate in parallel to increase and improve the efficiency of the signal processor The processor also includes an arrangement for controlling all processor cells on each diagonal of the array of cells As a result, not only can all cells on each diagonal operate in parallel but also each of the plurality of diagonals can operate in parallel for processing the same or different sets of input signals Thereby, a still further increase in the efficiency of the signal processor obtains

Random access memory system having high-speed serial data paths

Abstract: To overcome the bandwidth limitation of a random access memory (RAM), a shift register (20) is disposed within the memory array (1) such that the shift register lies parallel to the row lines and is connected to at least one of the bit lines contained within the array. Separate high-speed serial input and output lines (21, 22) are provided by the shift register. These lines are in addition to and operate independently of the slower speed input and output lines normally provided by the RAM. Through this arrangement, a row of data can be transferred to and from the memory array at a rate substantially faster than the single-bit access rate of the RAM.

An integrated multiprocessing array for time warp pattern matching

Abstract: Pattern matching by dynamic time warp has recently been widely applied in the fields of speech and visual pattern recognition. A new approach to this technique that is based on an orthogonal array of simple processing elements is presented. The approach emphasizes using parallel computation and pipelined data flow to achieve extremely high throughput. The internal architecture of the basic processing element and an integrated CMOS implementation are described. Simulation estimates indicate performance gains of up to 200:1 over existing techniques.

Functional verification in an interactive symbolic ic design environment

Abstract: This paper describes verification techniques that have been implemented as part of an interactive symbolic IC design system. Circuit analysis programs perform node extraction and gate decomposition. They generate both transistor and gate level circuit desriptions which are used as input to a transistor level digital MOS timing simulator. The extraction programs make use of an intermediate circuit description language which captures both geometric placement and circuit connectivity. All programs are written in the C programming language and run under the UNIX operating system. An example is included to demonstrate the operation of these various techniques.

A high speed array computer for dynamic time warping

Abstract: Dynamic time warping is an established technique for time alignment and comparison of speech segments in speech recognition. This paper describes a CMOS integrated array processor for computing the dynamic time warp algorithm. It allows many popular variations including LPC and frequency domain representations of speech. High speed is obtained by extensive pipelining, parallel computation, and simultaneous matching of multiple patterns. A realistic application using 40 nine-component LPC vectors per word permits 10,000 word comparisons per second or, equivalently, real time recognition of a 10,000 word vocabulary.