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Open AccessProceedings ArticleDOI

Virtual Grid Symbolic Layout

Neil Weste
- pp 224-232
TLDR
A new compaction strategy which uses the concept of a virtual grid is presented which is both simple and fast, an attribute which allows the designer to conveniently interact with the algorithm to optimize a layout.
Abstract
Free form or "stick" type symbolic layout provides a means of simplifying the design of IC subcircuits. To successfully utilize this style of layout, a complete design approach and the necessary tools to support this methodology are required. In particular, one of the requirements of such a design method is the ability to "compact" the loosely specified topology to create a set of valid mask data. This paper presents a new compaction strategy which uses the concept of a virtual grid. The compaction algorithm using the virtual grid is both simple and fast, an attribute which allows the designer to conveniently interact with the algorithm to optimize a layout. In addition to the compaction algorithm, methods used to create large building blocks will be described. The work described here is part of a complete symbolic layout system called MULGA which is written in the C programming language and resides on the UNIX operating system.

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Citations
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Proceedings ArticleDOI

Magic: A VLSI Layout System

TL;DR: The Magic layout system incorporates expertise about design rules and connectivity directly into the layout system in order to implement powerful new operations, including: a continuous design-rule checker that operates in background to maintain an up-to-date picture of violations.
Journal ArticleDOI

An Algorithm to Compact a VLSI Symbolic Layout with Mixed Constraints

TL;DR: This paper proposes an algorithm which uses a graph-theoretic approach to solve efficiently the compaction problem with mixed constraints.
Patent

Integrated electric design system with automatic constraint satisfaction

TL;DR: In this article, an electrical design system is described which integrates many analysis and synthesis tools in an environment of top-down circuit layout, including nMOS, CMOS, bipolar, printed circuit boards and others.
Journal ArticleDOI

A 70-MHz 8-bit/spl times/8-bit parallel pipelined multiplier in 2.5-/spl mu/m CMOS

TL;DR: Clock skew, a major problem encountered in high-speed pipelined architectures, is overcome by the use of a balanced clock distribution network all on metal, and by proper use of clock buffers.
References
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Proceedings ArticleDOI

Bristle Blocks: A Silicon Compiler

TL;DR: The Bristle Block system is an attempt to create a silicon compiler that will perform the majority of the implementation computation while placing a minimum set of constraints on the designer.
Journal ArticleDOI

Mulga — an interactive symbolic layout system for the design of integrated circuits

TL;DR: This paper describes a new compaction algorithm that allows the interactive editing, layout compaction, circuit connectivity extraction, parasitic audit, and timing simulation of MOS ICs within the symbolic domain through an intermediate circuit description language.
Journal ArticleDOI

A Dense Gate Matrix Layout Method for MOS VLSI

TL;DR: A rapid and systematic method for performing chip layout of VLSI circuits is described, which utilizes the configuration of a matrix composed of intersecting rows and columns to provide transistor placement and interconnections.

STICKS - A graphical compiler for high level LSl design

TL;DR: STICKS is a computer aided design system which frees the designer from the tedious aspects of IC design and allows him to concentrate on the more creative and necessarily human side of the design process.
Proceedings Article

STICKS - A graphical compiler for high level LSl design.

TL;DR: The STICKS system as discussed by the authors is a computer aided design system that allows the designer to free himself from the tedious aspects of IC design and allow him to concentrate on the more creative and necessarily human side of the design process.