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Neil Weste
Researcher at University of Adelaide
Publications - 84
Citations - 6229
Neil Weste is an academic researcher from University of Adelaide. The author has contributed to research in topics: Amplifier & CMOS. The author has an hindex of 24, co-authored 84 publications receiving 6057 citations. Previous affiliations of Neil Weste include University of South Australia & Cisco Systems, Inc..
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Book
CMOS VLSI Design : A Circuits and Systems Perspective
Neil Weste,David Money Harris +1 more
TL;DR: The authors draw upon extensive industry and classroom experience to introduce todays most advanced and effective chip design practices, and present extensively updated coverage of every key element of VLSI design, and illuminate the latest design challenges with 65 nm process examples.
Book
Principles of CMOS VLSI Design: A Systems Perspective
Neil Weste,K Eshraghian +1 more
TL;DR: CMOS Circuit and Logic Design: The Complemenatry CMOS Inverter-DC Characteristics and Design Strategies.
PRINCIPLES OF CMOS VLSI DESIGN A Systems Perspective Second Edition
Neil Weste,Kamran Eshraghian +1 more
Abstract: Introduction to CMOS Circuits. Introduction. MOS Transistors. MOS Transistor Switches. CMOS Logic. Circuit Representations. CMOS Summary. MOS Transistor Theory. Introduction. MOS Device Design Equation. The Complemenatry CMOS Inverter-DC Characteristics. Alternate CMOS Inverters. The Differential Stage. The Transmission Gate. Bipolar Devices. CMOS Processing Technology. Silicon Semiconductor Technology: An Overview. CMOS Technologies. Layout Design Rules. CAD Issues. Circuit Characterization and Performance Estimation. Introduction. Resistance Estimation. Capacitance Estimation. Inductance. Switching Characteristics. CMOS Gate Transistor Sizing. Power Consumption. Determination of Conductor Size. Charge Sharing. Design Margining. Yield. Scaling of MOS Transistor Dimensions. CMOS Circuit and Logic Design. Introduction. CMOS Logic Structures. Basic Physical Design of Simple Logic Gates. Clocking Strategies. Physical and Electrical Design of Logic Gates. 10 Structures. Structured Design Strategies. Introduction. Design Economics. Design Strategies. Design Methods. CMOS Chip Design Options. Design Capture Tools. Design Verification Tools. CMOS Test Methodolgies. Introduction. Fault Models. Design for Testability. Automatic Test Pattern Generation. Design for Manufacturability. CMOS Subsystem Design. Introduction. Adders and Related Functions. Binary Counters. Multipliers and Filter Structures. Random Access and Serial Memory. Datapaths. FIR and IIR Filters. Finite State Machines. Programmable Logic Arrays. Random Control Logic.
Proceedings ArticleDOI
Virtual Grid Symbolic Layout
TL;DR: A new compaction strategy which uses the concept of a virtual grid is presented which is both simple and fast, an attribute which allows the designer to conveniently interact with the algorithm to optimize a layout.
Journal ArticleDOI
The edge flag algorithm — A fill method for raster scan displays
B. D. Acland,Neil Weste +1 more
TL;DR: A new algorithm, based on a more exact definition of an object edge, is presented, implemented within the frame-store memory, which features high speed, in conjunction with minimal CPU memory requirements, making it ideally suited to hardware or microcode (firmware) implementation.