http://user.it.uu.se/~jarst116/slides/week4.pdf

Graph-Based Algorithms for Boolean Function Manipulation

This paper presents a novel test-data volume-compression methodology called the embedded deterministic test (EDT), which reduces manufacturing test cost by providing one to two orders of magnitude reduction in scan test data volume and scan test time. The presented scheme is widely applicable and easy to deploy because it is based on the standard scan/ATPG methodology and adopts a very simple flow. It is nonintrusive as it does not require any modifications to the core logic such as the insertion of test points or logic bounding unknown states. The EDT scheme consists of logic embedded on a chip and a new deterministic test-pattern generation technique. The main contributions of the paper are test-stimuli compression schemes that allow us to deliver test data to the on-chip continuous-flow decompressor. In particular, it can be done by repeating certain patterns at the rates, which are adjusted to the requirements of the test cubes. Experimental results show that for industrial circuits with test cubes with very low fill rates, ranging from 3% to 0.2%, these schemes result in compression ratios of 30 to 500 times. A comprehensive analysis of the encoding efficiency of the proposed compression schemes is also provided.

Embedded deterministic test

VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)

Test data compression consists of test vector compression on the input side and response, compaction on the output side This vector compression has been an active area of research This article summarizes and categories these techniques The focus is on hardware-based test vector compression techniques for scan architectures Test vector compression schemes fall broadly into three categories: code-based schemes use data compression codes to encode test cubes; linear-decompression-based schemes decompress the data using only linear operations (that is LFSRs and XOR networks) and broadcast-scan-based schemes rely on broadcasting the same values to multiple scan chains

https://users.ece.utexas.edu/~touba/research/dt06.pdf

Survey of Test Vector Compression Techniques

A system includes a semiconductor device. The semiconductor device includes a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single crystal silicon layer, wherein the at least one metal layer comprises copper or aluminum more than other materials; and a second single crystal silicon layer overlying the at least one metal layer. The second single crystal silicon layer comprises a plurality of second transistors arranged in substantially parallel bands. Each of a plurality of the bands comprises a portion of the second transistors along an axis in a repeating pattern.

System comprising a semiconductor device and structure

Post-silicon validation plays a critical role in exposing design errors in early silicon prototypes. Its effectiveness is conditioned by in-system application of functionally-compliant stimuli for extensive periods of time. This is achieved by expanding on-the-fly randomized functional sequences, which are subjected to user-programmable constraints. In this paper we present a method to extend the existing work for on-chip generation of functionally-compliant randomized sequences with support for sequential constraints.

On Supporting Sequential Constraints for On-Chip Generation of Post-silicon Validation Stimuli

Addressing lifetime performance degradation caused by circuit ageing has been a topic of active research for the past few years. In this paper we present a different perspective to this problem, by leveraging the presence of clock tuning elements that are commonly available in high-performance designs. By combining clock tuning elements with on-chip sensors for predicting setup/hold-time violations, we introduce a new clock tuning mechanism that operates on-the-fly and it maintains the maximum achievable performance in-system for each circuit sample affected by ageing.

In-system and on-the-fly clock tuning mechanism to combat lifetime performance degradation

Motivated by the difficulty of implementing pseudo-random built-in self-test (BIST) to non-BIST-ready intellectual properly (IP) cores, this paper introduces StreamBIST, a new low cost methodology for embedded deterministic test. By combining low overhead pseudo-random on-chip generation with external control for test pattern expansion, the proposed StreamBIST methodology provides maximum coverage for IP core compact and deterministic test sets. In addition to guaranteeing IP-protection, StreamBIST facilitates reduction in volume of test data, testing time, tester channel capacity requirements and it can seamlessly be integrated into the existing tool flows for modular system-on-a-chip (SOC) testing.

Embedded compact deterministic test for IP-protected cores

System-on-a-chip designs may contain user defined logic or embedded cores that cannot be wrapped for test purposes due to area constraints or timing violations. This paper discusses how these unwrapped logic blocks can be tested rapidly through the TestRail architecture using only the test control mechanism and the test instructions available through IEEE standard for embedded core test. A new test scheduling algorithm, which facilitates concurrent test of both unwrapped logic blocks and wrapped cores, is proposed and experiments show that it outperforms a previous approach when the available number of tester channels and/or the number of unwrapped logic blocks are small

On concurrent test of wrapped cores and unwrapped logic blocks in SOCs

This paper discusses the potential benefits of inserting scan chains (SCs) in hierarchical designs at the register-transfer level (RTL) of design abstraction. Using new algorithms for functional scan chain design, it is shown how tight timing constraints for design-for-test (DFT) planning at RTL can improve the performance of a circuit, when compared to its gate level counterpart, without any loss in testability.

Nicola Nicolici

Papers

On Supporting Sequential Constraints for On-Chip Generation of Post-silicon Validation Stimuli

In-system and on-the-fly clock tuning mechanism to combat lifetime performance degradation

Embedded compact deterministic test for IP-protected cores

On concurrent test of wrapped cores and unwrapped logic blocks in SOCs

Register-transfer level functional scan for hierarchical designs