http://user.it.uu.se/~jarst116/slides/week4.pdf

Graph-Based Algorithms for Boolean Function Manipulation

This paper presents a novel test-data volume-compression methodology called the embedded deterministic test (EDT), which reduces manufacturing test cost by providing one to two orders of magnitude reduction in scan test data volume and scan test time. The presented scheme is widely applicable and easy to deploy because it is based on the standard scan/ATPG methodology and adopts a very simple flow. It is nonintrusive as it does not require any modifications to the core logic such as the insertion of test points or logic bounding unknown states. The EDT scheme consists of logic embedded on a chip and a new deterministic test-pattern generation technique. The main contributions of the paper are test-stimuli compression schemes that allow us to deliver test data to the on-chip continuous-flow decompressor. In particular, it can be done by repeating certain patterns at the rates, which are adjusted to the requirements of the test cubes. Experimental results show that for industrial circuits with test cubes with very low fill rates, ranging from 3% to 0.2%, these schemes result in compression ratios of 30 to 500 times. A comprehensive analysis of the encoding efficiency of the proposed compression schemes is also provided.

Embedded deterministic test

VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)

Test data compression consists of test vector compression on the input side and response, compaction on the output side This vector compression has been an active area of research This article summarizes and categories these techniques The focus is on hardware-based test vector compression techniques for scan architectures Test vector compression schemes fall broadly into three categories: code-based schemes use data compression codes to encode test cubes; linear-decompression-based schemes decompress the data using only linear operations (that is LFSRs and XOR networks) and broadcast-scan-based schemes rely on broadcasting the same values to multiple scan chains

https://users.ece.utexas.edu/~touba/research/dt06.pdf

Survey of Test Vector Compression Techniques

A system includes a semiconductor device. The semiconductor device includes a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single crystal silicon layer, wherein the at least one metal layer comprises copper or aluminum more than other materials; and a second single crystal silicon layer overlying the at least one metal layer. The second single crystal silicon layer comprises a plurality of second transistors arranged in substantially parallel bands. Each of a plurality of the bands comprises a portion of the second transistors along an axis in a repeating pattern.

System comprising a semiconductor device and structure

This book is the first book that covers all asopects of power-constrained test solutions. It is a reflection of authors own research and also survey of the major contributions in this domain.

Power-constrained testing of VLSI circuits

The decisions on when to acquire debug data during post-silicon validation are determined by trigger events that are programmed into on-chip trigger units. In this paper, we investigate how to design trigger units that are both resource-efficient and runtime programmable. To achieve these two goals, we introduce new architectural features, as well as an algorithm for automatically mapping trigger events onto trigger units.

Resource-Efficient Programmable Trigger Units for Post-Silicon Validation

The size of on-chip trace buffers used for at-speed silicon debug limits the observation window in any debug session. Whenever the debug experiment can be repeated, we propose a novel architecture for at-speed silicon debug that enables a methodology where the designer can iteratively zoom only in the intervals containing erroneous samples. When compared to increasing the size of the trace buffer, the proposed architecture has a small impact on silicon area, while significantly reducing the number of debug sessions.

Interactive presentation: Low cost debug architecture using lossy compression for silicon debug

This paper introduces a new method to construct functional scan chains at the register-transfer level aimed at increasing the delay fault coverage when using the skewed-load test application strategy. It is shown how by consciously creating scan paths prior to logic synthesis, both the transition delay fault coverage and circuit speed can be improved.

Functional scan chain design at RTL for skewed-load delay fault testing

Post-silicon validation is an essential step in the design flow, which is needed to demonstrate that the implemented circuit meets its intended behavior. Due to lack of in-system controllability and observability, design-for-debug hardware is employed to aid post-silicon validation. A number of solutions have been proposed to implement the design-for-debug hardware, as well as to analyze the debug data that is acquired. Although the design entry is done at the register-transfer level, the existing approaches to aid post-silicon validation rely primarily on the information extracted from the gate level circuit descriptions. We anticipate that, as the design complexity continues to grow, extracting and processing circuit information at this level will become increasingly difficult. In this paper, we briefly summarize the known art and discuss some possible directions of investigation that can utilize high-level circuit descriptions to augment the existing solutions.

Nicola Nicolici

Papers

Power-constrained testing of VLSI circuits

Resource-Efficient Programmable Trigger Units for Post-Silicon Validation

Interactive presentation: Low cost debug architecture using lossy compression for silicon debug

Functional scan chain design at RTL for skewed-load delay fault testing

Design-for-debug for post-silicon validation: Can high-level descriptions help?