http://user.it.uu.se/~jarst116/slides/week4.pdf

Graph-Based Algorithms for Boolean Function Manipulation

This paper presents a novel test-data volume-compression methodology called the embedded deterministic test (EDT), which reduces manufacturing test cost by providing one to two orders of magnitude reduction in scan test data volume and scan test time. The presented scheme is widely applicable and easy to deploy because it is based on the standard scan/ATPG methodology and adopts a very simple flow. It is nonintrusive as it does not require any modifications to the core logic such as the insertion of test points or logic bounding unknown states. The EDT scheme consists of logic embedded on a chip and a new deterministic test-pattern generation technique. The main contributions of the paper are test-stimuli compression schemes that allow us to deliver test data to the on-chip continuous-flow decompressor. In particular, it can be done by repeating certain patterns at the rates, which are adjusted to the requirements of the test cubes. Experimental results show that for industrial circuits with test cubes with very low fill rates, ranging from 3% to 0.2%, these schemes result in compression ratios of 30 to 500 times. A comprehensive analysis of the encoding efficiency of the proposed compression schemes is also provided.

Embedded deterministic test

VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)

Test data compression consists of test vector compression on the input side and response, compaction on the output side This vector compression has been an active area of research This article summarizes and categories these techniques The focus is on hardware-based test vector compression techniques for scan architectures Test vector compression schemes fall broadly into three categories: code-based schemes use data compression codes to encode test cubes; linear-decompression-based schemes decompress the data using only linear operations (that is LFSRs and XOR networks) and broadcast-scan-based schemes rely on broadcasting the same values to multiple scan chains

https://users.ece.utexas.edu/~touba/research/dt06.pdf

Survey of Test Vector Compression Techniques

A system includes a semiconductor device. The semiconductor device includes a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single crystal silicon layer, wherein the at least one metal layer comprises copper or aluminum more than other materials; and a second single crystal silicon layer overlying the at least one metal layer. The second single crystal silicon layer comprises a plurality of second transistors arranged in substantially parallel bands. Each of a plurality of the bands comprises a portion of the second transistors along an axis in a repeating pattern.

System comprising a semiconductor device and structure

This paper investigates the application of computational methods via Satisfiability Modulo Theory (SMT) to the bit-width allocation problem for finite precision implementation of numerical calculations, specifically in the context of scientific computing where division frequently occurs. In contrast to the large body of work targeted at the precision aspect of the problem, this paper addresses the range problem where employing SMT leads to more accurate bounds estimation than those provided by other analytical methods, in turn yielding smaller bit-widths, and hence a reduction in hardware cost and/or increased parallelism, while maintaining robustness as is necessary for scientific applications.

Bit-Width Allocation for Hardware Accelerators for Scientific Computing Using SAT-Modulo Theory

This letter investigates the reasons for the current trade-off of test data volume for scan power dissipation in system-on-chip (SOC) testing, understands the conflict between the existing compression method and scan power minimization technique and proves that by using a new compression method this trade-off is unnecessary. When the new compression method is combined with scan reordering savings up to 97% in peak power and 99% in average power, as well as compression ratios of up to 95% are possible.

Simultaneous reduction in volume of test data and power dissipation for systems-on-a-chip

This paper explores the use of SAT-Modulo Theory in determination of bit-widths for finite precision implementation of numerical calculations, specifically in the context of scientific computing where division frequently occurs. Employing SAT-Modulo Theory leads to more accurate bounds estimation than those provided by other analytical methods, in turn yielding smaller bit-widths.

Finite precision bit-width allocation using SAT-modulo theory

Mixed-mode BIST offers complete fault coverage with short test application times and small test data requirements. Reducing power dissipation during testing is becoming necessary for decreasing the risks of reliability problems and manufacturing yield loss. Several techniques have been recently proposed for reducing power dissipation during BIST. The work presented addresses the problem of reducing power dissipation in mixed-mode BIST. A new mixed-mode test pattern generator is proposed with reduced power dissipation during test when compared with existing test pattern generators. This is achieved by combining the masking properties of AND/OR composition with LFSR reseeding. Extensive experiments were performed on several benchmark circuits using commercial synthesis and simulation tools to validate the efficiency and assess the overhead of the proposed solution. Experimental results show that reductions up to 20% in average power dissipation during test can be achieved when compared with traditional test pattern generators.

Dual multiple-polynomial LFSR for low-power mixed-mode BIST

Since pre-silicon functional verification is insufficient to detect all design errors, re-spins are often needed due to malfunctions that escape into the silicon. This paper presents an automated software solution to analyze the data collected during silicon debug. The proposed methodology analyzes the test sequences to detect suspects in both the spatial and the temporal domain. A set of software debug techniques are proposed to analyze the acquired data from the hardware testing and provide suggestions for the setup of the test environment in the next debug session. A comprehensive set of experiments demonstrate its effectiveness in terms of run-time and resolution.

/pdf/automated-data-analysis-solutions-to-silicon-debug-13c0gnzorw.pdf

Nicola Nicolici

Papers

Bit-Width Allocation for Hardware Accelerators for Scientific Computing Using SAT-Modulo Theory

Simultaneous reduction in volume of test data and power dissipation for systems-on-a-chip

Finite precision bit-width allocation using SAT-modulo theory

Dual multiple-polynomial LFSR for low-power mixed-mode BIST

Automated data analysis solutions to silicon debug