Nikolaos Bellas

TL;DR: In this paper, the authors focus on low-power design techniques for high-performance processors at the architectural and compiler levels, and propose a method that uses an additional minicache located between the I-Cache and the central processing unit (CPU) core and buffers instructions that are nested within loops and are continuously otherwise fetched from the ICache.

TL;DR: This paper uses OpenCL, an industry supported standard for writing programs that execute on multicore platforms and accelerators such as GPUs, and adapts OpenCL into a novel hardware design flow which efficiently maps coarse and fine-grained parallelism of an application onto an FPGA reconfigurable fabric.

TL;DR: This paper proposes a technique that uses an additional mini cache located between the I-Cache and the CPU core, and buffers instructions that are nested within loops and are continuously otherwise fetched from the I -Cache, and shows that the additional cache, dubbed L-Cache, is much smaller and simpler than theI-Cache when the compiler assumes the role of allocating instructions in it.

TL;DR: This work proposes, implements, and evaluates a series of run-time techniques for dynamic analysis of the program instruction access behavior, which are then used to preactively guide the access of the LO-Cache, an additional mini cache located between the instruction cache (I-Cache) and the CPU core.

TL;DR: This work extends the work proposed by J. Kin et al. (1997), in which an extra, small cache is inserted between the CPU data path and the L1 cache and serves to filter most of the references initiated from the CPU.