The issue of the energy shortage is affecting the entire planet. This is occurring because of massive population and industry growth around the world. As a result, the entire world is attempting to implement green networking systems and manufacture the power/energy efficient products. This research work discusses the green networking system technologies. This work introduces a power-efficient control unit (CU) design and implemented on the Zynq SoC (System on Chip) ultrascale field programmable gate array (FPGA). The VIVADO HLx Design Suite is used to simulate and analyze the CU model which is considered as one of the key components of central processing unit (CPU), used for data communication purposes. The CU is made suitable for the green communication by making it power-efficient. Therefore, the power consumption of the CU is analyzed for the various set frequency value ranging between 100 MHz and 5 GHz, and it is discovered that as the clock frequency rises up, the total power consumption also tends to get increased. The total power of the proposed model is reduced by 77.42%, 21.29%, and 17.93% from three models, respectively, being compared in the present paper. Final results shows that the CU is better suited to run at low frequencies to optimize power consumption.

/pdf/vlsi-implementation-of-green-computing-control-unit-on-zynq-2loi84cd0x.pdf

VLSI Implementation of Green Computing Control Unit on Zynq FPGA for Green Communication

Fast data communication is the need of today’s generation. This is because of the advancements and growth of technologies. This research work is about the implementation and analysis of data communication of Universal Asynchronous Receiver Transmitter (UART) on Kintex-7 Field Programmable Gate Array (FPGA) at different clock periods. The implementation is done on the VIVADO tool and analysis of data communication for different clock time is done by timing summary option available on the VIVADO tool. It is observed that data communication takes place in UART when the clock period is 3ns or more than 3ns because for the data transfer Worst Negative Slack (WNS) and Worst Hold Slack (WHS) both must be positive and Total Hold Slack (THS) and Total Negative Slack (TNS) should be 0.000. If the clock period is less than 3ns no data transfer will take place.

Effective Data Transmission with UART on Kintex-7 FPGA

The laser drivers are extremely important to be used to provide safe interface for the optical components attached
to the laser. In this paper, energy efficient laser driver circuit is design using field programming gate array (FPGA). The
laser driver is first designed using current mode logic (CML) technique, which is widely used for designing the optical
components. Then this design is implemented on FPGA using very large scale integration (VLSI). The laser driver
produces the energy efficient output using voltage scaling technique in which the core voltage of FPGA virtex-7 board is
reduced from 2.2 V (Peak core voltage of FPGA) to 0.5 V (base voltage of FPGA). By reducing core voltage of FPGA
virtex-7 from peak to base voltage the power consume by laser drivers is reduced up to 90% for 15 THz frequency.
Similarly, for less than 15 THz frequencies the power consumption is also reduced. The main advantage of designing this
energy efficient laser driver is that it will control the output of any high frequency semiconductor laser up to 15 THz
frequency. This energy efficient design of laser driver will be integrated with high frequency semiconductor laser to
produce green optical output for communication systems.

Energy efficient design of laser driver using field programming gate array

In this research, based on computing independent offloading set green communication, a mobile fusion mechanism for 5G network was indicated, to solve the problem of large-scale computing, limited resource and low utilization of 5G network. First, a 5G network architecture was designed for supporting autonomy, with the deployment of several edge terminals, multiple autonomous base stations and multiple autonomous control networks. Then, the multiple autonomous base stations were deployed evenly. Each user terminal device performs various kinds of business applications. And the information of their computing task size and resource requirements would be sent to the autonomous base station, which could autonomously control network. Secondly, to further improve the utilization of resources and reduce energy consumption, a green communication mechanism and mobile fusion mechanism were established by considering the channel characteristics and the diversity of resource status in the 5G network. Simulation results show that the proposed algorithm performs the following improvement real-time performance of 10%, throughput of 15%, convergence speed of 5%, energy efficiency and parallel computing efficiency of 8% than the reference (EURASIP J Embed Syst 2016(1):5, 2016).

Green communication mobile convergence mechanism for computing self-offloading in 5G networks

This brief is reporting a useful design to modulate threshold voltage and leakage current in single pocket fully depleted silicon on insulator. A comparative analysis has been made between the device without pocket and single pocket device. Since device size is in nanoscopic scale therefore a peak electric field occurs to mitigate this issue pocket is made. This work highlights the effects of variation in metal gate work function on threshold voltage and leakage current. Analysis shows the E-field distribution in single pocket device is much better than the E-filed distribution in the conventional device. On same metal gate work function 4.3 eV to 4.8 eV single pocket device has better switching speed and low leakage current than that of conventional device. The simulation of both devices has been handled by ALTAS TCAD tool.

Effect of Gate Metal Work Function on Leakage Current in Single Pocket FDSOI 28 nm Transistor

FIR Filter always remains in linear phase with the help of symmetric coefficient. This feature makes it ideal for phase-sensitive applications like data communications. Design of FIR filter with energy efficiency makes excellent sense to achieve energy efficiency in digital selected frequency module of communication. We are using scaling of output load from 5000 to 0 pF to show an effect of output load on both on-chip and off-chip power consumption of FIR filter design. 20 nm technology based FVA1156 package and Kintex-7 family ultra-scale FPGA is taken under reconsideration for implementation of our model. With the use of HSTL_II IO standards, there is 84.39 and 92.83% reduction in IOs power when we scale down capacitance from 5000 to 500 and 0 pF respectively. With the use of HSTL_I_18 IO standards, there is 72.48 and 80.13% reduction in total on-chip power when we scale down capacitance from 5000 to 500 and 0 pF respectively. Along with IOs power and total on-chip power, we have also analyzed Off-chip device power, junction temperature, thermal margin, and different dynamic power likes Signal power, logic power, and DSP power.

Scaling of Output Load in Energy Efficient FIR Filter for Green Communication on Ultra-Scale FPGA

In this particular work, we have implemented the algorithm of comparator on different version of FPGA like virtex-4, virtex-5, virtex-6, virtex-6(low power) and virtex-7. Using high performance Xilinx ISE software, we calculated the supply power and timing constraints like delay in timings from source pad to destination of the algorithm when implemented on different versions of FPGA.

/pdf/power-and-time-delay-analysis-of-simple-comparator-29sb3xgrvk.pdf

Power and Time Delay Analysis of Simple Comparator Implemented On Different Type of FPGA

The Video PHY controller offers an interface between transmitters/receivers and video ports. These video ports are categorized in HDMI or Displayport. HDMI Video PHY controller are mostly used for their high speed operation for high resolution graphics. However, the execution of high resolution graphics consumes more power, this creates a need of designing the low power design for Video PHY controller. In this paper, the performance of Video PHY controller is analyzed by comparing the power consumption of unidirectional and bi-directional IO Standard over 7 series FPGA. It is determined that total on-chip power is reduced for unidirectional IO Standard based Video PHY controller compared to bidirectional IO Standard based Video PHY controller. The most significant achievement of this work is that it is concluded that unidirectional IO Standard based Video PHY controller consume least standby power compared to bidirectional IO Standard based Video PHY controller. It is defined that for 6 GHz operated frequency Video PHY controller, the 32% total on-chip power is reduced using unidirectional IO Standard based Video PHY controller is less compared to bidirectional IO Standard based Video PHY controller. It is also demonstrated that 97% device static power i.e. standby mode power consumption is reduced using unidirectional IO Standard based Video PHY controller is less compared to bidirectional IO Standard based Video PHY controller. The proposed design will be to provide high resolution video processing at low standby power consumption using unidirectional IO Standard based Video PHY controller is less compared to bidirectional IO Standard based Video PHY controller. KeywordsPower Consumption, Static Power Consumption, Standby Power Consumption, Unidirectional and Bidirectional IO Standard, Video PHY Controller, 7 Series Field Prograaming Gate Array.

/pdf/performance-analysis-of-video-phy-controller-using-59cco7zww3.pdf

Performance Analysis of Video PHY Controller Using Unidirection and Bi-directional IO Standard via 7 Series FPGA

In Today's World it is very easy to share the information fast may be within seconds or even may be less However, the required data is shared so it is the main concern We share data over web and data is transferred in the form of packets How these data packets are transmitted is all concept of Networking This paper focuses on making of a packet counter that consumes least power for its operation Packet counters are used for counting data packets at transmitter and receiver end and hence finding the number of packets or data lost in whole process The Design is implemented for LVCOMS_25, LVDCI_25, SSTL_15 and HSTL_III I/O standards for Virtex6 Field Programmable Gate Array Percentage Change in power consumed is calculated by scaling frequency and hence efficient packet counter is achieved

/pdf/reduction-in-power-consumption-of-packet-counter-on-virtex-6-2fcx1icpmk.pdf

Reduction in power consumption of packet counter on VIRTEX-6 FPGA by frequency scaling

Traffic blockage is one of the major issues faced by world today. That can be road traffic or air traffic or even water traffic .Traffic Controllers provide the right direction by providing a rule for any kind of Vehicles. The idea goes around designing traffic light controller system which utilizes least amount of power and is well tested in hardware using Xilinx Virtex6 Field Programmable gate array. FPGA designs are not only cheaper than ASIC designs but have many positive features like speed and performance. So the factors that contribute to power consumption for family of HSTL are studied for the purpose of making Light Controller Efficient using VHDL. Keywords-Traffic Light Controller, ASIC Designs, Virtex6, Speed, Power, HSTL

/pdf/fpga-based-efficient-design-of-traffic-light-controller-1zfhb7io4c.pdf

Nisha Pandey

Papers

Scaling of Output Load in Energy Efficient FIR Filter for Green Communication on Ultra-Scale FPGA

Power and Time Delay Analysis of Simple Comparator Implemented On Different Type of FPGA

Performance Analysis of Video PHY Controller Using Unidirection and Bi-directional IO Standard via 7 Series FPGA

Reduction in power consumption of packet counter on VIRTEX-6 FPGA by frequency scaling

FPGA Based Efficient Design of Traffic Light Controller using Frequency Scaling for Family of HSTL