How have Japanese companies become world leaders in the automotive and electronics industries, among others? What is the secret of their success? Two leading Japanese business experts, Ikujiro Nonaka and Hirotaka Takeuchi, are the first to tie the success of Japanese companies to their ability to create new knowledge and use it to produce successful products and technologies. In The Knowledge-Creating Company, Nonaka and Takeuchi provide an inside look at how Japanese companies go about creating this new knowledge organizationally. The authors point out that there are two types of knowledge: explicit knowledge, contained in manuals and procedures, and tacit knowledge, learned only by experience, and communicated only indirectly, through metaphor and analogy. U.S. managers focus on explicit knowledge. The Japanese, on the other hand, focus on tacit knowledge. And this, the authors argue, is the key to their success--the Japanese have learned how to transform tacit into explicit knowledge. To explain how this is done--and illuminate Japanese business practices as they do so--the authors range from Greek philosophy to Zen Buddhism, from classical economists to modern management gurus, illustrating the theory of organizational knowledge creation with case studies drawn from such firms as Honda, Canon, Matsushita, NEC, Nissan, 3M, GE, and even the U.S. Marines. For instance, using Matsushita's development of the Home Bakery (the world's first fully automated bread-baking machine for home use), they show how tacit knowledge can be converted to explicit knowledge: when the designers couldn't perfect the dough kneading mechanism, a software programmer apprenticed herself withthe master baker at Osaka International Hotel, gained a tacit understanding of kneading, and then conveyed this information to the engineers. In addition, the authors show that, to create knowledge, the best management style is neither top-down nor bottom-up, but rather what they call "middle-up-down," in which the middle managers form a bridge between the ideals of top management and the chaotic realities of the frontline. As we make the turn into the 21st century, a new society is emerging. Peter Drucker calls it the "knowledge society," one that is drastically different from the "industrial society," and one in which acquiring and applying knowledge will become key competitive factors. Nonaka and Takeuchi go a step further, arguing that creating knowledge will become the key to sustaining a competitive advantage in the future. Because the competitive environment and customer preferences changes constantly, knowledge perishes quickly. With The Knowledge-Creating Company, managers have at their fingertips years of insight from Japanese firms that reveal how to create knowledge continuously, and how to exploit it to make successful new products, services, and systems.

The knowledge-creating company

Come with us to read a new book that is coming recently. Yeah, this is a new coming book that many people really want to read will you be one of them? Of course, you should be. It will not make you feel so hard to enjoy your life. Even some people think that reading is a hard to do, you must be sure that you can do it. Hard will be felt when you have no ideas about what kind of book to read. Or sometimes, your reading material is not interesting enough.

Design Of Integrated Circuits For Optical Communications

In the present scheme of the world, the problem of shortage of power is seen across the world which can be a vulnerability to various communication securities. The scope of proposed research is that it is a step towards completing green communication technology concepts. In order to improve energy efficiency in communication networks, we designed UART using different nanometers of FPGA, which consumes the least amount of energy. This shortage is happening because of expanding of industries across the world and the rapid growth of the population. Therefore, to save the power for our upcoming generation, the globe is moving towards the concept and ideas of green communication and power-/energy-efficient gadget. In this work, a power-efficient universal asynchronous receiver transmitter (UART) is implemented on 28 nm Artix-7 field-programmable gate array (FPGA). The objective of this work is to reduce the power utilization of UART with the FPGA device in industries. To do this, the same authors have used voltage scaling techniques and compared the results with the existing FPGA works.

/pdf/energy-efficient-uart-design-on-fpga-using-dynamic-voltage-3d13wy2h.pdf

Energy-Efficient UART Design on FPGA Using Dynamic Voltage Scaling for Green Communication in Industrial Sector

The issue of the energy shortage is affecting the entire planet. This is occurring because of massive population and industry growth around the world. As a result, the entire world is attempting to implement green networking systems and manufacture the power/energy efficient products. This research work discusses the green networking system technologies. This work introduces a power-efficient control unit (CU) design and implemented on the Zynq SoC (System on Chip) ultrascale field programmable gate array (FPGA). The VIVADO HLx Design Suite is used to simulate and analyze the CU model which is considered as one of the key components of central processing unit (CPU), used for data communication purposes. The CU is made suitable for the green communication by making it power-efficient. Therefore, the power consumption of the CU is analyzed for the various set frequency value ranging between 100 MHz and 5 GHz, and it is discovered that as the clock frequency rises up, the total power consumption also tends to get increased. The total power of the proposed model is reduced by 77.42%, 21.29%, and 17.93% from three models, respectively, being compared in the present paper. Final results shows that the CU is better suited to run at low frequencies to optimize power consumption.

/pdf/vlsi-implementation-of-green-computing-control-unit-on-zynq-2loi84cd0x.pdf

VLSI Implementation of Green Computing Control Unit on Zynq FPGA for Green Communication

Fault tolerant control of wind turbines with an adaptive output feedback sliding mode controller

There are many areas of communication and network, which have open scope to use FIR filter. Therefore, energy efficient FIR filter will increase lifetime of network and FIR filter with less delay and latency will increase performance of network. In this work, we are going to design an FIR filter that will energy efficient as well as faster than traditional design. Three different FPGA and SOC are taken under consideration and our design is implemented on these four ICs and we find the most energy efficient architecture and also find the architecture that will deliver highest performance among these four architectures taken under consideration. There is 47.74% reduction in latency when we migrate our FIR Filter design from 28 nm process technology based seven series architecture to 20 nm process technology based ultrascale architecture. When we analyze power dissipation of Artix-7, Kintex-7, Zynq and Ultrascale FPGA then we conclude that Zynq 7000 All programmable SOC is power hungry architecture and Kintex ultrascale architecture is the most energy efficient architecture that dissipates 20.86% less power than Zynq 700 All programmable SOC. For performance evaluation, we have taken benchmark C code of FIR provide by Xilinx. We transform that C code into HDL using Vivado HLS 2016.2 before power analysis on Vivado 2016.2. Ultrascale FPGA is generally used for packet processing in 100G networking and heterogeneous wireless infrastructure.

Performance Evaluation of FIR Filter After Implementation on Different FPGA and SOC and Its Utilization in Communication and Network

Variable speed wind turbine is a complex and nonlinear system, a sophisticated control is required to meet the challenges posed by these systems. This paper is presenting a pitch regulation strategy based on LQG (Linear Quadratic Gaussian) to regulate turbine at its rated power and to reject the effect of disturbance acting on its rotor blades by wind. CART2 (Control Advanced Research Turbine) linear model is produced/generated by FAST (Fatigue, Aerodynamics, Structures and Turbulence) code to test its simulation on MATLAB/Simulink and various results are compared. The designed controller provide better disturbance rejection performance as compared to PID controller.

LQG controller design for pitch regulated variable speed wind turbine

Disturbance Accommodation Control (DAC) is used to model and simulate a system with known disturbance wave- form. This paper presents a control scheme to mitigate the effect of disturbances by using collective pitch control for the above- rated wind speed (Region III) for a variable speed wind turbine. We have used Linear Quadratic Regulator (LQR) to obtain full state feedback gain, disturbance feedback gain is calculated independently and then estimator gain is achieved by pole- placement technique in the DAC augmented plant model. The reduced order model (two-mass model) of wind turbine is used and 5MW National Renewable Energy Laboratory (NREL) wind turbine is used in this research. We have shown comparison of results relating to pitch angle, drive train torsion and generator speed obtained by a PID controller and DAC. Simulations are performed in MATLAB/Simulink. The results are compared with PID controller for a step wind and also for turbulent wind disturbance. DAC method shows better regulation in output power and less fatigue of drive train in the presence of pitch actuator limits. Proposed controller tested on wind turbine shows better robustness and stability as compared to PID. The paper describes practical experiences to develop a new DC power plant controller user interface based on human- centered design ideas.

DAC with LQR Control Design for Pitch Regulated Variable Speed Wind Turbine

Stub Series Terminated Logic (SSTL) is an Input/output standard. It is used to match the impedance of line, port and device of our design under consideration. Therefore, selection of energy efficient SSTL I/O standard among available different class of SSTL logic family in FPGA, plays a vital role to achieve energy efficiency in design under test (DUT). Here, DUT is ROM. ROM is an integral part of processor. Therefore, energy efficient design of RAM is a building block of energy efficient processor. We are using Verilog hardware description language, Virtex-6 FPGA, and Xilinx ISE simulator. We are operating ROM with the highest operating frequency of 4th generation i7 processor to test the compatibility of this design with the latest hardware in use. When there is no demand of peak performance, then we can save 74.5% clock power, 75% signal power, and 30.83% I/O power by operating our device with 1GHz frequency in place of 4GHz. There is no change in clock power and signal power but SSTL2_H_DCI having 80.24% 83.38% 62.92% and 76.52% and 83.03% more I/O power consumption with respect to SSTL2_I, SST18_I, SSTL2_I_DCI, SSTL2_II, and SSTL15 respectively at 3.3GHz.

/pdf/sstl-i-o-standard-based-environment-friendly-energyl-5ddelse5cx.pdf

SSTL I/O Standard based environment friendly energyl efficient ROM design on FPGA

FIR Filter always remains in linear phase with the help of symmetric coefficient. This feature makes it ideal for phase-sensitive applications like data communications. Design of FIR filter with energy efficiency makes excellent sense to achieve energy efficiency in digital selected frequency module of communication. We are using scaling of output load from 5000 to 0 pF to show an effect of output load on both on-chip and off-chip power consumption of FIR filter design. 20 nm technology based FVA1156 package and Kintex-7 family ultra-scale FPGA is taken under reconsideration for implementation of our model. With the use of HSTL_II IO standards, there is 84.39 and 92.83% reduction in IOs power when we scale down capacitance from 5000 to 500 and 0 pF respectively. With the use of HSTL_I_18 IO standards, there is 72.48 and 80.13% reduction in total on-chip power when we scale down capacitance from 5000 to 500 and 0 pF respectively. Along with IOs power and total on-chip power, we have also analyzed Off-chip device power, junction temperature, thermal margin, and different dynamic power likes Signal power, logic power, and DSP power.

D. M. Akbar Hussain

Papers

Performance Evaluation of FIR Filter After Implementation on Different FPGA and SOC and Its Utilization in Communication and Network

LQG controller design for pitch regulated variable speed wind turbine

DAC with LQR Control Design for Pitch Regulated Variable Speed Wind Turbine

SSTL I/O Standard based environment friendly energyl efficient ROM design on FPGA

Scaling of Output Load in Energy Efficient FIR Filter for Green Communication on Ultra-Scale FPGA