We present a theoretical analysis, design, and experimental characterization of a CMOS image sensor with pixel-level ΣΔ oversampling analog-to-digital conversion (ADC). The design employs five transistors per-pixel to implement a charge-based ΣΔ ADC at each pixel. In the current design a dynamic regenerative latch comparator is divided into an input transistor, which is contained within each pixel, and the remaining comparator structure shared among the pixels of each column. A charge feedback digital-to-analog converter (DAC) is implemented at each pixel with a three-transistor structure. As opposed to more traditional CMOS image sensors, this image sensor architecture is suitable for implementations in advanced low supply voltage CMOS technologies since its dynamic range is not affected by the reduction of the pixel reset voltage. In addition, similar to the readout methods in low power random access memory designs, this pixel readout architecture does not employ any active amplifiers which allows for low static power operation. Experimental characterization of a prototype fabricated in a 0.35 μm silicided CMOS technology is presented. The estimated power consumption of the fully integrated 128 × 128 imager including decimation filters and I/O interface is 60 nW/pixel at 30 frames per second for 8-bits per-pixel. A peak signal-to-noise ratio of 52 dB and intra-scene dynamic range of 74 dB were measured. The dynamic range was extended to 91 dB through control of the in-pixel DAC supply voltage over the range of 0.8 V-3.3 V.

Low Power, High Dynamic Range CMOS Image Sensor Employing Pixel-Level Oversampling $\Sigma\Delta$ Analog-to-Digital Conversion

An optimum design theory to clarify a possible limit of achieving both high conversion gain (CG) and full well capacity (FWC) at the same time in a CMOS image sensor with a lateral overflow integration capacitor (LOFIC) in a pixel is discussed. The possible limit of both high CG and high FWC is theoretically derived from a signal-to-noise-ratio (SNR) formula at a switching point from a low light signal (S1) to a bright one (S2). Based on this theory, a 1/4-in VGA-format 5.6-mum-pixel-pitch CMOS image sensor has been fabricated through a 0.18-mum 2P3M CMOS technology. A high-quality wide-dynamic-range image sensing has been demonstrated with no significant visible noise, achieving over 32 dB of SNR for an 18% gray card.

Optimum Design of Conversion Gain and Full Well Capacity in CMOS Image Sensor With Lateral Overflow Integration Capacitor

A complementary metal-oxide-semiconductor (CMOS) image sensor with low-noise global shuttering and a dual-shuttering mode is presented. The developed two-stage charge transfer pixel enables noise canceling by means of true correlated double sampling. The implemented prototype demonstrates for the first time that a noise level of less than three electrons can be achieved in a global-shutter CMOS image sensor while attaining high shutter efficiency of 99.7%. In the dual-shuttering mode, both a pinned storage diode signal and a floating diffusion signal are used for desirable functions such as wide-dynamic-range imaging, motion detection, and dual consecutive snapshot imaging.

A Two-Stage Charge Transfer Active Pixel CMOS Image Sensor With Low-Noise Global Shuttering and a Dual-Shuttering Mode

A 1/3-inch, 800H x 600v pixels, 5.6 x 5.6 mum2 color CMOS image sensor with three photocurrent integrations in pixel photodiodes, pixel lateral overflow capacitors and column capacitors fabricated in a 0.18 mum 2P3M CMOS technology has been reported. The image sensor operates using photodiode integrations and lateral overflow integrations in low light condition and achieves a wide dynamic range (DR) performance of around 100 dB in its one exposure. The wide DR performance in one exposure makes high S/N ratios at the signal switching points in the multiple exposures. The CMOS image sensor also operates using the column capacitor integration in very bright light condition. In the column capacitor integration, the photocurrents generated at the photodiodes are directly integrated at the column capacitors in each column line. The combination of two exposures using the photodiode integrations and the lateral overflow integrations and one exposure using the column capacitors leads to the whole linear photo-electric conversion responses from low light to very bright light region. The fabricated image sensor achieves a high S/N ratio, a fully linear response and over 180 dB DR in the incident light ranging from about 1.4 x 10-2 lx to about 2.4 x 107 lx.

A Wide DR and Linear Response CMOS Image Sensor With Three Photocurrent Integrations in Photodiodes, Lateral Overflow Capacitors, and Column Capacitors

A wide variety of image sensors have been developed
for numerous applications ranging from consumer imaging and cell
phones to space imaging, but in virtually every domain there is an
ever present need for improved image quality and reduced power
consumption. Most CMOS image sensors now include on-chip analog to
digital (A/D) conversion to enable easier integration into a
variety of camera platforms. Nearly all of these employ Nyquist
rate A/D converters, ranging from designs that share one A/D
converter for the entire imaging array to designs that effectively
have a separate ADC for each pixel. In this work we explore the
alternative of employing an oversampling sigma-delta A/D converter
at each pixel. Technology scaling leads to lower supply voltages,
which in turn affects the dynamic range and the signal-to-noise
(SNR) ratio of the image sensor. We show that sigma-delta A/D
conversion enables further supply voltage reduction without
decreasing the sensor‘s sensitivity and the SNR. We also
demonstrate a sigma-delta image sensor implementation with reduced
analog circuit complexity in comparison to earlier efforts.
Furthermore, the sigma-delta modulator is insensitive to the
inevitable electronic noise at the input of the comparator, which
leads to improved light sensitivity. In this work we explore a
specific implementation of the sigma-delta image sensor that may be
capable of reaching the theoretical limit of detecting a single
photon-generated electron during the exposure
time.

Image Sensors Employing Oversampling Sigma-Delta Analog-to-Digital Conversion with High Dynamic Range and Low Power

A 1/3-inch, 800H times 600v pixels, 5.6 times 5.6 mum2 color CMOS image sensor with three photocurrent integrations in pixel photodiodes, pixel lateral overflow capacitors and column capacitors fabricated in a 0.18 mum 2P3M CMOS process has been reported. It achieves high S/N ratio and fully linear response and over 180 dB dynamic range performances in the incident light range from about 1.4times10-2 Ix to about 2.4times107 Ix.

A Wide DR and linear response CMOS image sensor with three photocurrent integrations in photodiodes, lateral overflow capacitors and column capacitors

Operation methods for high frame rate, linear response, wide dynamic range (DR) and high SNR in a CMOS image sensor are discussed. The high frame rate operation is realized by the optimum design of the floating diffusion capacitor, the lateral overflow integration capacitor, the column integration capacitor and the integration periods of multiple voltage and current readout operations. The color CMOS image sensor which consists of the 1/3-inch, 800H × 600V pixels and 5.6-μm pixel pitch with a buried pinned-photodiode, a transfer switch, a reset switch, a lateral overflow switch, a lateral overflow integration capacitor, a photocurrent readout switch, a source follower transistor and a pixel select switch in each pixel has been fabricated by 0.18-μm 2P3M CMOS technology. The image sensor operates the total frame rate of 13-fps with three-time voltage readout operations and one current readout operation and have realized full linear photoelectric conversion responses, over 20-dB SNR for the image of the 18-% gray card at all integration operation switching points and the over 200-dB DR.© (2008) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

A linear response 200-dB dynamic range CMOS image sensor with multiple voltage and current readout operations

A wide dynamic range 64x64 CMOS image sensor with 20x20um 2 pixel that combines a lateral-overflow integration voltage-readout operation with the current readout operation from the buried photo-diode hasbeen developed.In the voltage readout operation,an over 160-dB dynamic range image with a linear response isobtained from sequential electronic shutter operations from 1/30 s to 1/130 ks with a dynamic range of about 100-dB within a light intensity range from about 10 -2lx to 106lx.In addition,an over 200-dB dynamic range perform-ance of up to 108lx or more with few time exposures in the high illuminance region is made possible by combiningit with the current reading operation.More than 40 dB for all noises,including photon shot noise,occurs around all the switching points.

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An over 200-dB dynamic range CMOS image sensor combining a lateral overflow integration with photo-current readout operation

We discuss the operation methods for keeping a high S/N ratio at all switching points in multiple exposures and for shorting the total integration time of a wide dynamic range (DR) lateral overflow integration capacitor (LOFIC) CMOS image sensor that combines electric-charge voltage conversions in a pixel and a column capacitor. We have used these methods on a color LOFIC CMOS image sensor. This sensor had a pixel pitch of 5.6-um and the number of effective pixels was 800 (H) x 600 (V). It was made by using 0.18-um 2P3M CMOS technology. Fully linear responses were obtained, as well as a DR of 207 dB. Furthermore, the S/N ratio was 26-dB for the image of 18% gray card at all the switching points between the multiple exposures. The total exposure time was1/13-sec and was obtained by three photoelectric conversion operations at FD and LOFIC capacitors and one photoelectric conversion operation in the column capacitor.

A Mulitiple-Exposure, Linear Response, Wide-Dynamic-Range CMOS Image Sensor Combining Electric-charge Voltage Conversions in Pixel Capacitor and Column Capacitor

Noriko Ide

Papers

A Wide DR and Linear Response CMOS Image Sensor With Three Photocurrent Integrations in Photodiodes, Lateral Overflow Capacitors, and Column Capacitors

A Wide DR and linear response CMOS image sensor with three photocurrent integrations in photodiodes, lateral overflow capacitors and column capacitors

A linear response 200-dB dynamic range CMOS image sensor with multiple voltage and current readout operations

An over 200-dB dynamic range CMOS image sensor combining a lateral overflow integration with photo-current readout operation

A Mulitiple-Exposure, Linear Response, Wide-Dynamic-Range CMOS Image Sensor Combining Electric-charge Voltage Conversions in Pixel Capacitor and Column Capacitor