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Nuwan Jayasena
Researcher at Stanford University
Publications - 5
Citations - 908
Nuwan Jayasena is an academic researcher from Stanford University. The author has contributed to research in topics: Memory bandwidth & Supercomputer. The author has an hindex of 5, co-authored 5 publications receiving 886 citations.
Papers
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Proceedings ArticleDOI
Smart Memories: a modular reconfigurable architecture
TL;DR: Simulations of the mappings show that the Smart Memories architecture can successfully map two very different machines at opposite ends of the architectural spectrum, the Imagine stream processor and the Hydra speculative multiprocessor, with only modest performance degradation.
Proceedings ArticleDOI
Merrimac: Supercomputing with Streams
William J. Dally,Francois Labonte,Abhishek Das,Pat Hanrahan,Jung Ho Ahn,Jayanth Gummaraju,Mattan Erez,Nuwan Jayasena,Ian Buck,Timothy James Knight,Ujval J. Kapasi +10 more
TL;DR: The design of Merrimac is sketched, a streaming scientific computer that can be scaled from a $20K 2 TFLOPS workstation to a $ 20M 2 PFLOPS supercomputer and the results of some initial application experiments on this architecture are presented.
Proceedings ArticleDOI
Stream register files with indexed access
TL;DR: A register file for streams (SRF) that allows arbitrary, indexed accesses is presented that provides speedups of 1.03x to 4.1x and memory bandwidth reductions of up to 95% over sequential SRF access for a set of benchmarks representative of data-parallel applications with irregular accesses.
Book
Memory hierarchy design for stream computing
William J. Dally,Nuwan Jayasena +1 more
TL;DR: A stream register file architecture that enables indexed, arbitrary access patterns, allowing a wider range of data reuse to be captured in on-chip, software-managed memory compared to current stream processors, and introduces epoch-based cache invalidation to improve the performance of hardware-managed caches for stream computing.
Proceedings ArticleDOI
Fault Tolerance Techniques for the Merrimac Streaming Supercomputer
TL;DR: This paper explores soft-error fault tolerance in the context of computeintensive architectures, which differ significantly from their control-intensive CPU counterparts, and proposes schemes to conserve the critical and costly off-chip bandwidth and on-chip storage resources while maintaining high peak and sustained performance.