Clock distribution networks synchronize the flow of data signals among synchronous data paths. The design of these networks can dramatically affect system-wide performance and reliability. A theoretical background of clock skew is provided in order to better understand how clock distribution networks interact with data paths. Minimum and maximum timing constraints are developed from the relative timing between the localized clock skew and the data paths. These constraint relationships are reviewed, and compensating design techniques are discussed. The field of clock distribution network design and analysis can be grouped into a number of subtopics: 1) circuit and layout techniques for structured custom digital integrated circuits; 2) the automated layout and synthesis of clock distribution networks with application to automated placement and routing of gate arrays, standard cells and larger block-oriented circuits; 3) the analysis and modeling of the timing characteristics of clock distribution networks; and 4) the scheduling of the optimal timing characteristics of clock distribution networks based on architectural and functional performance requirements. Each of these areas is described the clock distribution networks of specific industrial circuits are surveyed and future trends are discussed.

Clock distribution networks in synchronous digital integrated circuits

As the gap between processor and memory speeds continues to widen, methods for evaluating memory system designs before they are implemented in hardware are becoming increasingly important. One such method, trace-driven memory simulation, has been the subject of intense interest among researchers and has, as a result, enjoyed rapid development and substantial improvements during the past decade. This article surveys and analyzes these developments by establishing criteria for evaluating trace-driven methods, and then applies these criteria to describe, categorize, and compare over 50 trace-driven simulation tools. We discuss the strengths and weaknesses of different approaches and show that no single method is best when all criteria, including accuracy, speed, memory, flexibility, portability, expense, and ease of use are considered. In a concluding section, we examine fundamental limitations to trace-driven simulation, and survey some recent developments in memory simulation that may overcome these bottlenecks.

Trace-driven memory simulation: a survey

The current status of VLSI layout and directions for future research are addressed, with emphasis on the authors' own work Necessary terminology and definitions and, whenever possible, a precise formulation of the problems are provided Placement and floorplanning for both the sea-of-gates and building-block designs are examined The former emphasizes the connectivity specification, whereas the latter must also consider module shape and size Global routing based on a method of successive cuts on a chip is discussed This is a hierarchical top-down approach that is useful for both of the above designs A two-dimensional detailed routing problem and the rip-up and rerouting problem are also discussed The field of computational geometry and its application to layout-in particular, to gridless routing and compaction-are reviewed, and layout engines are considered >

Recent advances in VLSI layout

Researchers have identified a core set of program transformations that are effective in array-based loop nest optimization: these loop transformations include interchange, skewing, reversal and tiling. Researchers have studied these transformations individually for their legality and effect on parallelism and memory hierarchy performance; but they have not discussed in any detail how to choose the combination of transformations that best optimizes a loop nest. Other researchers have taken another approach: they consider each loop nest as a whole, applying an elegant matrix theory of loop nest transformation, but one that is only applicable to a limited class of loop nests, those whose dependences can be expressed as distance vectors. In this limited context, the problems of memory hierarchy improvement and parallelization are simplified, but their approach has not been extended to apply to general loop nests.
We have combined the elegance of the matrix theory with the generality of general dependence vectors into a new theory of loop transformation. This theory has enabled us to apply an algorithmic approach to solving optimization goals. Using this theory, we have developed efficient algorithms for the compiler to use to improve memory hierarchy utilization and parallelism of general loop nests. The parallelization improving algorithm maximizes the degree of parallelism within a loop nest, at either a coarse or fine granularity. The locality improving algorithm uses the same theory, and also reuse information about array accesses within loop nests, to guide the transformation process. The parallelization and locality improvement algorithms are unified so that locality and parallelism can be improved simultaneously without significantly reducing either.
We have implemented versions of these algorithms in Stanford's SUIF compiler and performed experimentation on the Perfect Club and the NASA kernels. We have found compiler locality improvement to significantly improve performance when applicable. We have also demonstrated a tremendous sensitivity of performance on tile size for tiled codes on machines with direct-mapped or low set associativity caches.

Improving locality and parallelism in nested loops

Cache miss characterization models such as the three Cs model are useful in developing schemes to reduce cache misses and their penalty. In this paper we propose the OPT model that uses cache simulation under optimal (OPT) replacement to obtain a finer and more accurate characterization of misses than the three Cs model. However, current methods for optimal cache simulation are slow and difficult to use. We present three new techniques for optimal cache simulation. First, we propose a limited lookahead strategy with error fixing, which allows one pass simulation of multiple optimal caches. Second, we propose a scheme to group entries in the OPT stack, which allows efficient tree based fully-associative cache simulation under OPT. Third, we propose a scheme for exploiting partial inclusion in set-associative cache simulation under OPT. Simulators based on these algorithms were used to obtain cache miss characterizations using the OPT model for nine SPEC benchmarks. The results indicate that miss ratios under OPT are substantially lower than those under LRU replacement, by up to 70% in fully-associative caches, and up to 32% in two-way set-associative caches.

/pdf/efficient-simulation-of-caches-under-optimal-replacement-4g3dkk623c.pdf

Efficient simulation of caches under optimal replacement with applications to miss characterization

Two CAD tools, checkT/sub c/ and minT/sub c/, for timing verification and optimal clocking are introduced. Both tools are based on a new timing model of synchronous digital circuits. The model has the following features: (1) it is general enough to handle arbitrary multiphase clocking; (2) complete, in the sense that it captures signal propagation along short as well as long paths in the logic; (3) extensible to make it relatively easy to incorporate 'complex' latching structures; and (4) notationally simple to make it amenable to analytic treatment in some important special cases. These tools are being used to help in the design of a 4 ns gallium arsenide micro-supercomputer. >

CheckT/sub c/ and minT/sub c/: timing verification and optimal clocking of synchronous digital circuits

The authors present a succinct formulation of the timing constraints for latch-controlled synchronous digital circuits. It is shown that the constraints are mildly nonlinear. The equivalence of the nonlinear optimal cycle time calculation problem to an associated and simpler linear programming (LP) problem is proved. A LP-based algorithm which is guaranteed to obtain the optimal cycle time for arbitrary circuits controlled by a general class of multiphase overlapped clocks is presented. The formulation and an initial implementation of the algorithm on some example circuits are illustrated. >

Analysis and design of latch-controlled synchronous digital circuits

A new formulation of the timing constraintss for latch-controlled synchronous digital circuits is presented. The authors show that the constraints are mildly nonlinear, and prove the equivalence of the nonlinear optimal cycle time calculation problem to an associated and simpler linear programming (LP) problem. An LP-based algorithm is presented which is guaranteed to obtain the optimal cycle time for arbitrary circuits controlled by a general class of multi-phase overlapped clocks. An initial implementation of this LP-based solution procedure is illustrated for two example circuits. >

This paper describes an experiment in which parallel routing is performed on a medium grained hypercube parallel processor having 64 processing elements. Each node is a complete 32-bit computer with 128 K-bytes of memory and is connected to the other nodes via a direct hypercube interconnection network. A new parallel routing algorithm was developed to exploit this parallel structure. It is a three step algorithm consisting of a global routing step, a boundary crossing placement step, and a detailed routing step. All steps can be performed in parallel. When applied to a standard benchmark it was able to route 95 % of the wires. The algorithm was also executed on a large mainframe computer using the same benchmark. The execution time was compared to that for the hypercube. The hypercube was about three times as fast.

A Preliminary Investigation into Parallel Routing on a Hypercube Computer

A description is given of work to develop a prototype microcomputer that will realize the best of both the supercomputer and the microprocessor traditions. It does so by using GaAs MESFET enhancement/depletion direct-coupled FET logic, a high-speed technology that has good integration density, and state-of-the-art packaging technology to prevent chip crossings from dominating the overall speed of the system. The focus of the research reported is the relationship between hardware implementations and emerging technologies. The MIPS Computer Systems instruction set was implemented to bound the architectural options and to eliminate the need to develop compilers and operating systems. Efforts are concentrated on developing the processor and cache. The resulting system will be a general-purpose computer that runs a conventional Unix environment and supports standard programming languages and networking protocols. The machine will significantly accelerate execution of the existing large base of application software. >

O.A. Olukotun

Papers

CheckT/sub c/ and minT/sub c/: timing verification and optimal clocking of synchronous digital circuits

Analysis and design of latch-controlled synchronous digital circuits

Analysis and design of latch-controlled synchronous digital circuits

A Preliminary Investigation into Parallel Routing on a Hypercube Computer

The design of a microsupercomputer