DRAM trench capacitors formed by, inter alia, deposition of conductive material into a trench or doping the semiconductor region in which the trench is defined.

Dynamic random access memory trench capacitors

A storage electrode has a truncated-conical “pipe-shaped” top section having a small inner diameter, mounted on a cylindrical base section having a large inner diameter. To fabricate the storage electrode, a buried contact plug is formed on a first insulating layer on a wafer, and an etching stop layer and a second insulating layer are formed on the first insulating layer. A third insulating layer is formed on the second insulating layer after implanting impurities into the second insulating layer. An opening is formed by anisotropically etching the third insulating layer and the second insulating layer using a photoresist pattern as an etching mask. A cleaning process is carried out such that the second insulating layer exposed through the opening is isotropically etched. After depositing polysilicon along a profile of the second and third insulating layers to a uniform thickness, the remaining third and second insulating layers are removed.

Storage electrode of a semiconductor memory device and method for fabricating the same

An etch stop layer is formed over a surface of an interlayer insulating layer and over a surface of a conductive plug extending at a depth from the surface of the interlayer insulating layer. A lower mold layer is deposited over the etch stop layer, and a wet etch rate of the lower mold layer is adjusted by adding dopants to the lower mold layer during formation of the lower mold layer, and by annealing the lower mold layer. An upper mold layer is then deposited over the surface of the lower mold layer, such that a wet etch rate of the upper mold layer is less than the adjusted wet etch rate of the lower mold layer. The upper mold layer, the lower mold layer and the etch stop layer are then subjected to dry etching to form an opening therein which exposes at least a portion of the surface of the contact plug. Then a wet etching of the upper mold layer and the lower mold layer is performed so as to increase a size of the opening at the lower mold layer and so at to expose a surface portion of the etch stop layer adjacent the surface of the conductive plug. A conductive material is then deposited over the surface of the opening in the upper and lower mold layers to define a capacitor electrode.

One-cylinder stack capacitor and method for fabricating the same

The present invention relates to a novel method for fabricating a storage capacitor designed as a trench or a stacked capacitor and is used in particular in a DRAM memory cell. The method includes steps of forming a lower, metallic capacitor electrode, a storage dielectric and an upper capacitor electrode. The lower, metallic capacitor electrode is formed in a self-aligned manner on a silicon base material in such a way that uncovered silicon regions are first produced at locations at which the lower capacitor electrode will be formed, and then metal silicide is selectively formed on the uncovered silicon regions.

Method for fabricating a storage capacitor

A method of manufacturing a deep trench capacitor. A deep trench is formed in a substrate. A conformal capacitor dielectric layer and a first conductive layer are sequentially formed, completely filling the deep trench. The first conductive layer has a seam. The first conductive layer is etched to open up the seam. A collar oxide layer is formed over the interior surface of the deep trench. A collar liner layer is formed over the collar oxide layer inside the deep trench. Using the collar liner layer as a mask, the collar oxide material above the first conductive layer and within the seam is removed. The collar liner layer is removed. Finally, a second conductive layer and a third conductive layer are sequentially formed inside the deep trench.

Method of manufacturing deep trench capacitor

Trench capacitors are fabricated utilizing a method which results in a metallic nitride as a portion of a node electrode in a lower region of the trench. The metallic nitride-containing trench electrode exhibits reduced series resistance compared to conventional trench electrodes of similar dimensions, thereby enabling reduced ground rule memory cell layouts and/or reduced cell access time. The trench capacitors of the invention are especially useful as components of DRAM memory cells having various trench configuration and design.

Low resistance fill for deep trench capacitor

A semiconductor device is presented which is directed to a method of forming embedded DRAM and logic devices, where the DRAM devices are formed in bulk, single crystalline semiconductor regions (24) and logic devices are formed in silicon-on-insulator ("SOI") regions (26) and where buried, doped glass to smooth the 250 nm step at the edge of the DRAM array region, making it easier to perform the lithography used to pattern the deep trenches (32) for storage in the bulk region. The resulting structure is also disclosed.

Vertical transistor trench capacitor DRAM with SOI logic devices

Method of forming vertical transistor trench capacitor DRAM with SOI logic devices

Reduced scale structures of improved reliability and/or increased composition options are enabled by the creation and use of quantum conductive recrystallization barrier layers. The quantum conductive layers are preferably used in trench capacitors between: the interface (58) of conductive strap (56) and substrate (60); the interface (62) of trench electrode (50) and strap (56); or the interface (64) of collar oxide (48) and strap (56) to act as recrystallization barriers. The quantum conductive barrier layer can be selected from the group consisting of silicon nitride, silicon oxynitride, alumina, germanium oxide and yttria-stabilized zirconia, and can have a thickness of about 5-30 A.

o Ibm United Kingdom Ltd. Mandelman

Papers

Low resistance fill for deep trench capacitor

Vertical transistor trench capacitor DRAM with SOI logic devices

Method of forming vertical transistor trench capacitor DRAM with SOI logic devices

Quantum conductive recrystallization barrier layers for semiconductor devices