This paper proposes a new behavioral model to treat memory effects in nonlinear power amplifiers (PAs) Phenomena such as asymmetries in lower and upper intermodulation terms, and variation of AM/AM and AM/PM, depending on signal history, are often observed in high-power PAs To treat these phenomena, this paper presents a model based on the previously developed memory polynomial model The contribution made in this paper is to augment the memory polynomial model to include a sparse delay tap structure that reduces the parameter space required for accurate model identification A figure-of-merit, called the memory effect ratio, is defined to quantify the relative level of distortion due to memory effects, as compared to the memoryless portion Another figure-of-merit is defined as the memory effect modeling ratio, which quantifies the degree to which the PA memory effects have been accounted for in the model This new technique is validated using a variety of RF PAs, including an 880-MHz and a 21-GHz high-power laterally diffused metal-oxide semiconductor PA and various signals such as two-tone, eight-tone, and IS-95B signals

Behavioral modeling of nonlinear RF power amplifiers considering memory effects

An RF switch circuit and method for switching RF signals that may be fabricated using common integrated circuit materials such as silicon, particularly using insulating substrate technologies. The RF switch includes switching and shunting transistor groupings to alternatively couple RF input signals to a common RF node, each controlled by a switching control voltage (SW) or its inverse (SW_), which are approximately symmetrical about ground. The transistor groupings each comprise one or more insulating gate FET transistors connected together in a “stacked” series channel configuration, which increases the breakdown voltage across the series connected transistors and improves RF switch compression. A fully integrated RF switch is described including control logic and a negative voltage generator with the RF switch elements. In one embodiment, the fully integrated RF switch includes an oscillator, a charge pump, CMOS logic circuitry, level-shifting and voltage divider circuits, and an RF buffer circuit.

Switch Circuit and Method of Switching Radio Frequency Signals

A method and apparatus for use in improving the linearity characteristics of MOSFET devices using an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one exemplary embodiment, a circuit having at least one SOI MOSFET is configured to operate in an accumulated charge regime. An accumulated charge sink, operatively coupled to the body of the SOI MOSFET, eliminates, removes or otherwise controls accumulated charge when the FET is operated in the accumulated charge regime, thereby reducing the nonlinearity of the parasitic off-state source-to-drain capacitance of the SOI MOSFET. In RF switch circuits implemented with the improved SOI MOSFET devices, harmonic and intermodulation distortion is reduced by removing or otherwise controlling the accumulated charge when the SOI MOSFET operates in an accumulated charge regime.

Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink

A method and apparatus for use in a digitally tuning a capacitor in an integrated circuit device is described. A Digitally Tuned Capacitor DTC is described which facilitates digitally controlling capacitance applied between a first and second terminal. In some embodiments, the first terminal comprises an RF+ terminal and the second terminal comprises an RF− terminal. In accordance with some embodiments, the DTCs comprise a plurality of sub-circuits ordered in significance from least significant bit (LSB) to most significant bit (MSB) sub-circuits, wherein the plurality of significant bit sub-circuits are coupled together in parallel, and wherein each sub-circuit has a first node coupled to the first RF terminal, and a second node coupled to the second RF terminal. The DTCs further include an input means for receiving a digital control word, wherein the digital control word comprises bits that are similarly ordered in significance from an LSB to an MSB.

Method and apparatus for use in digitally tuning a capacitor in an integrated circuit device

The noise figure in low-noise radio frequency cascode amplifiers using narrow-band input-impedance matching is exhaustively analyzed and accurate equations are derived which fit simulated results well. Moreover, the effect on noise performance of different impedance-matching approaches is discussed and fundamental limitations caused by specific matching networks are pointed out. Finally, an improved matching network is proposed which reduces dominant noise components, greatly improving noise figure. By using the same process parameters, calculations and simulations show that the proposed matching arrangement achieves a noise figure at 0.9 GHz, which is about 0.9-dB better than the state-of-the-art solution.

Noise figure and impedance matching in RF cascode amplifiers

A 1.9 GHz-band internally matched Si-MMIC front-end, fabricated in standard 0.8 /spl mu/m BiCMOS process, was developed. This IC front-end contains a MOSFET T/R switch, a two-stage BJT low noise amplifier (LNA), and a down converter BJT mixer. Since the circuits are monolithically integrated on a low resistivity Si substrate, the coplanar waveguide (CPW) type spiral inductors are used to reduce the dielectric loss of on-chip matching circuits. The T/R switch has measured insertion loss of 2.5 dB and isolation of 25.5 dB at 0/3 V control voltage. The two-stage LNA has gain of 17.1 dB and noise figure (NF) of 2.9 dB at 2 V, 4 mA dc supply. The mixer has conversion gain of 5.9 dB and NF of 15 dB at 2 V, 1.7 mA dc supply. The measured performance of the fabricated Si-MMIC front-end indicates the possibility of application to mobile communication handset terminals.

L-band internally matched Si-MMIC front-end

The transfer characteristic of relative phase of the third-order intermodulation distortion (IM/sub 3/) of a GaAs FET amplifier is measured and analyzed. The measurement system and method are also described. For drives in the weakly nonlinear region, the measured relative phase of IM/sub 3/ is equal to that of the carrier and is in agreement with the analysis results using Volterra-series representation. For drives in the saturation region, the measured relative phase of IM/sub 3/ versus the input power moves drastically compared with that of the carrier and is in agreement with numerical analysis using discrete Fourier transform. Comparison between measured and analytical results shows the drastic move of IM/sub 3/ relative phase is caused by the generation of IM/sub 3/ due to AM-PM conversion. The measured results and the measurement method are useful for the design and adjustment of predistortion-type linearizers for GaAs FET high-power amplifiers.

Transfer characteristic of IM/sub 3/ relative phase for a GaAs FET amplifier

The use of high resistivity Si substrates, instead of the conventional low resistivity Si substrate, enables one to reduce the loss of spiral inductor for the on-chip matching circuit by 61% at 1.9 GHz and by 78% at 5.8 GHz and to improve gain and noise performance of the BJT. These improvements are explained as the reduction of dielectric loss of substrate by referring to equivalent circuit model extraction. The fabricated 1.9 GHz-band on-chip matching LNA performs 13.4 dB gain, 1.9 dB NF with 2 V, 2 mA DC power and 5.8 GHz-band LNA performs 6.9 dB gain, 3.3 dB NF with 3 V, 3 mA DC power.

1.9 GHz/5.8 GHz-band on-chip matching Si-MMIC low noise amplifiers fabricated on high resistive Si substrate

Measured transfer characteristic of relative phase of the third order intermodulation distortion (IM/sub 3/) of a GaAs FET amplifier is described. The measurement system and method are also described. For drives in the weakly nonlinear region, the measured relative phase of IM/sub 3/ is equal to that of carriers, and agrees with the analysis result based on Volterra-series representation. For drives in the saturation region, the measured relative phase of IM/sub 3/ versus the input power is larger than that of carrier's relative phase. The measured results and the measurement method are useful for the design and adjustment of predistortion type linearizer for GaAs FET high power amplifiers.

An 800 MHz-band front-end multi-chip module (MCM) was developed for antenna diversity type handset terminals of the Japanese personal digital cellular systems (PDC). This module includes a dual input GaAs FET low noise amplifier (LNA) with a switching function, a SAW filter and a GaAs dual-gate FET mixer. Since the dual input LNA works as two independent LNAs and a SPDT switch, a very small size and a low production cost front-end MCM can be obtained. The package size of this MCM is 0.13 cc. With -10 dBm local input power and a supply d.c. current of 4.0 mA and a d.c. voltage of 3 V, a noise figure of 3.2 dB and a conversion gain of 22.5 dB were obtained.

O. Ishida

Papers

L-band internally matched Si-MMIC front-end

Transfer characteristic of IM/sub 3/ relative phase for a GaAs FET amplifier

1.9 GHz/5.8 GHz-band on-chip matching Si-MMIC low noise amplifiers fabricated on high resistive Si substrate

Transfer characteristic of IM/sub 3/ relative phase for a GaAs FET amplifier

An 800 MHz-band front-end MCM for antenna diversity type mobile communication handset terminals