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Design Of Analog Cmos Integrated Circuits

This paper presents design and implementation of a 9-bit folding and interpolation ADC using 0.35 µm CMOS C35B4 model under AMS-HIT Kit Library. The complete system consists of two main blocks. One of them is 4-bit flash ADC, which is based on the so-called Threshold Inverter Quantization (TIQ) technique. This part forms the coarse part of the data conversion process. The second one is the 5-bit fine ADC part of the converter. This block includes comparator, analog pre-processing and interpolation units. The designed converter works with 5 V power supply, and has analog input range of 3.4 Vpp. Analog input bandwidth is 1 MHz with clock frequency of 2 GHz for the digital part. The linearity measures of the converter include 2.9 LSB of DNL and 6.3 LSB of INL. The main purpose of this work is to investigate the possibility of employing TIQ technique in designing folding and interpolation type of ADCs. Although, the linearity measures are not satisfying for 9-bit case, the authors believe that this case study will serve as a preferred reference for the researchers who are willing to use TIQ technique in designing fast ADCs other than flash scheme especially.

	 

	Key words: Threshold inverter quantization, flash analog-to-digital converter, folding and interpolation analog-to-digital converter.

https://www.africaneditors.org/journal/SRE/full-text-pdf/42260-132948

Employing Threshold Inverter Quantization (TIQ) technique in designing 9-Bit folding and interpolation CMOS analog-to-digital converters (ADC)

In this work, we introduce a MoS2-based field effect transistor that can alternately operate either as a p-type or an n-type semiconductor in the same device. The proposed device is built with an adjustable threshold voltage (Vth), which can be varied by adding a layer of plasma-oxidized dielectric at the top gate structure. This facilitates a surplus of oxygen due to the relatively thin grown dielectric layer and the creation of negative charges in that layer instead of the usual ones of positive polarization in the bottom dielectric layer. Consequently, the Vth shifts and the top gate structure switches from the typical n-type to p-type while the n-type behaviour remains in the application of the bottom-gate voltages. The Vth can be tuned further by applying a gate pulse input at the top gate. Accordingly, we have demonstrated complementary logic inverters with adjustable device characteristics that are controllable by the polarity of charges induced in the device's oxide layer. This is a big step towards the concurrent implementation of both n-type and p-type characteristics in a single device.

Polarity-controllable MoS2 transistor for adjustable complementary logic inverter applications

This paper was presented the design of a threshold inverter quantized (TIQ) comparator in flash analog to digital converter. The TIQ-comparator has a high speed response; however this circuit involves a lot of transistors hence wasteful power consumption. The design is intended to obtain a low-power TIQ-comparator and reduces the area of the chip in 0.18 µm CMOS technology. The method was proposed to set each of the transistor channel length for the threshold voltage difference gained of the inverter each in the TIQ-comparator and adding a transistor as compensation to overcome the limitations of the length channel expansion due to the body effect influence. This method has reduced the drain current of CMOS transistors; hence the power dissipation can be reduced. The event has achieved low power dissipation of 31.14 µW and a chip size of 1065 µm2 with 0 to 0.6 V input signal condition.

An Improved A Low Power CMOS TIQ Comparator Flash ADC

In this paper, a novel multiplexer based thermometer to binary Code Encoder For 4 Bit Flash ADC is proposed. The proposed encoder design uses 2:1 multiplexes (MUX) and 2 input XOR gates for converting thermometer code to binary code. Initially 2:1 MUX are used to convert the thermometer code to equivalent gray code. The resulting gray code is then converted to the binary code using XOR gates. Low power consumption is achieved in the proposed design with the grounding concept and avoiding the additional inverters compared to the conventional encoder design. The proposed encoder is implemented in 180 nm CMOS, N-well technology with 1.8 V supply voltage and was simulated using Cadence Spectre simulator. Simulation results shows reduction in power up to 60% when compared with conventional encoder architectures. The proposed design has a figure-of-merit (FOM) of 13.28 fJ with the propagation delay of 0.5180 ns.

Design of novel multiplexer based thermometer to binary code encoder for 4 bit flash ADC

In this article, a novel 10-bit two-step flash A/D converter architecture based on the threshold inverter quantization technique, TIQ is presented The simulation results include 15V analog input range, 30 MHz input bandwidth, and 250 mWatts of power consumption at maximum sampling rate of 500 Ms/s The process parameter and temperature variation analysis of the converter is especially included The DC simulation results show linearity measures of less than 01 LSB DNL and INL for each 5-bit flash core The active chip area is 14mm2 in 05mum CMOS technology

A 10-Bit 500Ms/s Two-Step Flash ADC

This paper presents a 5-bit flash analog-to-digital converter design using the 0.18-m m Taiwan Semiconductor Manufacturing Company's CMOS technology library. The designed system consists of 2 main blocks, a comparator array, and a digital decoder. The digital decoder contains a latch, 1-of-N decoder, and fat-tree encoder units. The 1-of-N decoder is implemented using 2 \times 1 multiplexers. As a result, the active die area and the power consumption are reduced, in addition to an increase in the sampling frequency. The power supply voltage range for the overall system is \pm 0.9 V. For testing purposes, a ramp signal of between --0.45 V and 0.7 V is applied to the converter input. The sampling frequency is 5 Gs/s. The simulation results include a maximum power consumption of 28 mW, integral nonlinearity values of between --0.65 least significant bits (LSB) and +0.01 LSB, differential nonlinearity values of between --0.3 LSB and +0.13 LSB, and an active die area of 0.1 mm2.

https://journals.tubitak.gov.tr/elektrik/issues/elk-13-21-sup.1/elk-21-sup.1-12-1201-114.pdf

A 5-bit 5 Gs/s flash ADC using multiplexer-based decoder

The main purpose of this study is to investigate the so-called threshold inverter quantisation (TIQ) technique from a MOS transistor mismatch point of view. The logic threshold voltage values on the voltage transfer characteristics of three different area-sized CMOS cascaded inverters located on four different locations around a TIQ-based 5b Flash ADC are measured over 40 fabricated samples in a 0.5 μm CMOS process to investigate the intra-die and inter-die mismatch effects. Based on the test results, the worst case inter-die and intra-die standard deviations occur (as 70 mV and 80 mV, respectively) when (W n/W p) has the minimum design value of (W n/W p = 3.6 μm/23.6 μm). If the mean value of percent–standard deviations are chosen as the comparison parameter, then the comparator having minimum size of transistors exhibits the worst case matching property for having 2.91% of mean percent–standard deviation value for the intra-die case. This work concludes that the suggested resolution values for TIQ-based...

MOS mismatch effects on TIQ comparators

RF devices have frequency, power and duration setting options, it is important to make sure that the device meets the targeted values at the head output. This study was made to evaluate the RF devi...

Oktay Aytar

Papers

Employing Threshold Inverter Quantization (TIQ) technique in designing 9-Bit folding and interpolation CMOS analog-to-digital converters (ADC)

A 10-Bit 500Ms/s Two-Step Flash ADC

A 5-bit 5 Gs/s flash ADC using multiplexer-based decoder

MOS mismatch effects on TIQ comparators

Effects of device variables to radiofrequency (RF) applications.