A color cathode-ray tube including a main lens section comprising an anode to which an anode voltage is applied, and a focus electrode. The focus electrode has first type of focus electrode group to which a first focus voltage is applied, and a second type of focus electrode group to which a second focus voltage is applied which is obtained by superposing on a predetermined voltage a voltage that changes depending upon the deflecting amount of the electron beams. Between the first type of focus electrode group and the second type of focus electrode group are formed in a dynamic lens and an electrostatic quadrupole lens. Three electron beam passage holes are formed in the electrodes that form the dynamic lens and the centers for the outer electron beam passage holes in the first type of focus electrode group are deviated relative to the centers of the outer electron beam passage holes in the second type of focus electrode group in the horizontal direction. The electrostatic quadrupole lens exhibits different intensities for the outer electron beams relative to the center electron beam.

Color cathode ray tube

A computer system shares memory between multiple processors by dividing the memory into a plurality of sections, subsections, and banks, and by providing a memory path between each processor and each section of memory. Each processor may generate references to the memory from any one of four ports, which are multiplexed to the memory paths and onto the sections of memory. The system provides that each processor has an associated register in each subsection of memory and that each processor can make no more than one reference to a subsection at a time. Reference conflict resolution means are provided at the processor level to arbitrate conflicts between ports in the processors attempting to reference the same section or subsection in the memory. Reference conflict resolution means are provided at the subsection level of the memory to arbitrate conflicts between different processors attempting to reference the same banks of memory.

Apparatus for sharing memory in a multiprocessor system

PURPOSE:To ensure the use of a vector register with high efficiency under a simple control by providing individually plural vector registers which can perform both writing and reading at a time via a vector data processor and write/ read address registers. CONSTITUTION:An OP code designates the multiplication to perform the instructions which designate vector registers VR0, VR1 and VR2 through an arithmetic result store operand part, the 1st operand part and the 2nd operand part respectively. Then the OP code designates the addition to deliver the instructions which designate VR3, VR0 and VR4 through the arithmetic result store operand part, the 1st operand part, the 2nd operand part respectively. Thus the accesses of the VR0 overlap each other. However the former instruction is equal to a writing action carried out by the control of a writing address register 11, and the latter instruction is equal to a reading action done by the control of a reading address register 21. Thus a simultaneous access is possible with both instructions. As a result, the latter instructions are started before the execution is through with the former instructions.

Vector data processor

A vector operation processing apparatus utilizes a plurality of vector registers in a pipeline computer architecture. The vector registers store ordered data elements which are processed in a pipelined vector operation unit in response to a vector instruction which designates selected ones of the vector registers. An input selection circuit is utilized for writing results of the operation performed by the pipelined vector operation unit into the vector registers which are designated by the vector instruction. A write control device is used for causing the writing operation to be performed exclusively on the plurality of vector registers in response to an indication by the vector instruction.

Vector processing apparatus

PURPOSE:To speed up instruction processing by inhibiting reading of a corresponding vector factor while a mask bit read out in such a way that mask bit reading proceeds the reading of the corresponding vector factor is indicating the arithmetic to be restrained. CONSTITUTION:At the time of starting a vector instruction, a mask vector address register 12, an inter-vector factor distance registers 41-43 and vector factor registers 49-51 are initialized. The value of an address addition value register 13 is added to the value of the register 12 so as to read out the mask vector from a memory device 2 and stored in a mask vector register 32. A priority encoder 33 counts arithmetic inhibiting bits from the top of the mask vector until the initial arithmetic indicating bit can be found. A multiplying circuit 45 multiplies an inter-vector factor distance by the number of arithmetic inhibiting bits, an address adder circuit 53 adds a difference address to read the vector factor from a memory device 5. The read-out vector factor is transferred to an arithmetic device, thereby speeding up the instruction processing.

Vector instruction processor

PURPOSE:To omit read/write of unnecessary element data and to improve processing efficiency by reading previously a mask register and by detecting nonfulfilment about elememts of ones interleaved. CONSTITUTION:Element data read from a vector register designated in an operand part of an instruction are stored successively in a read register 2, and it is then, after being delayed by a buffer register 4 by one-time slot, added to an arithmetic pipeline 5. Further, element data that are designated and read out in an next operand part are successively set in a read register 3 and are inputted into the line 5. An arithmetic result outputted from said pipeline is set in a write register 1, further is written in a vector register designated in the operand part of the instruction. Further, a mask element read from an operand register designated in the mask operand part of the instruction is read out and is set in a register 6, further the output is inputted into the line 5, thereby determining execution of an operation by the logic of the mask element.

PURPOSE:To transmit an instruction to an operator by a simple control, by constituting a vector register consisting of plural elements, of plural banks each. CONSTITUTION:A bank timing shift register 22 is operated in order to prescribe a bank timing, and its contents are shifted to the right at every 1 cycle. When a flip-flop (a) is logical ''1'', the bank timing is made A, and when a flip-flop (b) is logical ''1'', the bank timing becomes B. An adder using timing storage part 24 stores a bank timing used for access of #0 element by an adder 10, and a multiplier using timing storage part 25 stores a bank timig used for access of #0 element by a multiplier 11. When a vector instruction is received, an instruction control part 8 detects an idle bank timing, and informs to the processing pipe line concerned that the instruction should be executed by use of said idle bank timing.

Vector data processing device

PURPOSE:To access an element, by prescribing a timing for accessing an element of a vector register of each bank, providing a controlling circuit for controlling whether the prescribed timing is used or not, and selecting the prescribed timing. CONSTITUTION:From the center of the first and second bits and the center of the fourth and fifth bits of a shift register 20, the respective outputs are inputted to an addition register 20, the respective outputs are inputted to an addition processing circuit 22 and a multiplication processing circuit 23. On the other hand, an output of a decoder 21 which has received an instruction as an input is also inputted to the circuit 22 and 23. Also, outputs of use displaying circuit 26, 27 of timings ABC, DEF are inputted to the circuits 22, 23, respectively. For instance, the addition processing circuit 22 detects that the ABC timing is being used and the DEG timing is unused, and if the next instruction inputted to the decoder 21 is an adding instruction, its adding instruction is received by the addition processing circuit 22, and the addition processing is started by the DEF timing.

Data processing control system

PURPOSE:To execute the vector operation efficiently, by supplying element data of the same number in memory banks to a pipeline operating part simultaneously in a pipeline operating device. CONSTITUTION:In a pipeline operating device, elements of vector registers are interleaved and stored in memory banks 3-6 divided into plural vector registers, and element data of the same number are stored in the same memory bank. The same element data in memory banks are supplied to pipeline oprating parts 27 and 29 simultaneously and are operated. Consequently, a specific memory bank is not occupied during vector calculation. Since elements of the same number are set in the same memory bank, the control is facilitated.

Pipeline operating device

PURPOSE:To realize efficient processing by making access timing to a vector register coincide with access timing to a mask register. CONSTITUTION:A storage control section 3 loads desired element data to a main storage device 1 by means of a load processing section 4 and stores the desired element data to the device 1 by means of a store processing section 5 in accordance with an instruction from an instruction control section 6. An operation processing section 9 reads out desired element data from a vector register 7 and performs multiplication and/or addition on the data, and then, writes the result in the register in accordance with an instruction from the controlling section 6. At this time, mask data are also read out from a mask register 8 and used for making mask control. Furthermore, the processing section 9 fetches desired mask data from the register 8 and performs operation on them, and then, writes the result in the register 8, in accordance with an instruction from the control section 6.

Okuya Shigeaki

Papers

Vector data processor

Vector data processing device

Data processing control system

Pipeline operating device

Register access control system