A computer system shares memory between multiple processors by dividing the memory into a plurality of sections, subsections, and banks, and by providing a memory path between each processor and each section of memory. Each processor may generate references to the memory from any one of four ports, which are multiplexed to the memory paths and onto the sections of memory. The system provides that each processor has an associated register in each subsection of memory and that each processor can make no more than one reference to a subsection at a time. Reference conflict resolution means are provided at the processor level to arbitrate conflicts between ports in the processors attempting to reference the same section or subsection in the memory. Reference conflict resolution means are provided at the subsection level of the memory to arbitrate conflicts between different processors attempting to reference the same banks of memory.

Apparatus for sharing memory in a multiprocessor system

The present invention concerns a system for quickly latching (1) an interchangeable and removable part (2) relative to a fixed part (3), particularly a strap relative to a watch casing or clasp, a shoulder strap, or a handbag clasp or portfolio clasp, performed by means of a retractable transversal axis constituting a male connective element disposed at the end of the removable part (2), capable of engaging at the ends thereof with two corresponding housings (6) of the fixed part (3), constituting a female connective element (7) built into the fixed part (3), said connective elements being complementary to engage by nesting within one another, characterised in that the male connective element (5) is integrated into a casing (8), which is itself integrated into the removable part (2), and is formed by the ends of two axis portions (4a, 4b), diverging from one another in the same transversal plane and freely passing through two lateral housings (9) of the casing (8), the ends (4a',4b') of each axis portion (4a,4b) extending by elastically deformable linking arms (10), symmetrically converging onto a central body (11) itself extending by elastic return means (12) supported within the back (13) of the casing (8), which constantly push against the assembly, in an equally permanent locking position of the axis portions (4a, 4b), the unlocking thereof being performed by means of an outside manual control unit (14) passing through the casing (8) via a pinhole (15) and rigidly connected with the central body (11) on which it pulls, to drive said body in an axial motion (F) capable of causing two convergent, parallel transversal motions (F1 and F2) of the axis portions (4a, 4b).

A system for quickly latching an interchangeable removable part, particularly a watchstrap

A liquid-crystal resin composition comprising 100 parts by weight of a partially aromatic liquid-crystal polyester and/or a partially aromatic liquid-crystal polyester amide, 0.001 to 5 parts by weight of at least one compound selected from among phosphorous acid, hypophosphorous acid and metal salts of these acids and 0.01 to 10 parts by weight of red phosphorus. This composition is useful as a material for engineering plastics because of its low anisotropy, and excellent flame retardancy, thermal resistance and hydrolytic resistance.

Liquid-crystal resin composition and moldings

PURPOSE:To ensure the use of a vector register with high efficiency under a simple control by providing individually plural vector registers which can perform both writing and reading at a time via a vector data processor and write/ read address registers. CONSTITUTION:An OP code designates the multiplication to perform the instructions which designate vector registers VR0, VR1 and VR2 through an arithmetic result store operand part, the 1st operand part and the 2nd operand part respectively. Then the OP code designates the addition to deliver the instructions which designate VR3, VR0 and VR4 through the arithmetic result store operand part, the 1st operand part, the 2nd operand part respectively. Thus the accesses of the VR0 overlap each other. However the former instruction is equal to a writing action carried out by the control of a writing address register 11, and the latter instruction is equal to a reading action done by the control of a reading address register 21. Thus a simultaneous access is possible with both instructions. As a result, the latter instructions are started before the execution is through with the former instructions.

Vector data processor

A vector operation processing apparatus utilizes a plurality of vector registers in a pipeline computer architecture. The vector registers store ordered data elements which are processed in a pipelined vector operation unit in response to a vector instruction which designates selected ones of the vector registers. An input selection circuit is utilized for writing results of the operation performed by the pipelined vector operation unit into the vector registers which are designated by the vector instruction. A write control device is used for causing the writing operation to be performed exclusively on the plurality of vector registers in response to an indication by the vector instruction.

Vector processing apparatus

PURPOSE:To omit read/write of unnecessary element data and to improve processing efficiency by reading previously a mask register and by detecting nonfulfilment about elememts of ones interleaved. CONSTITUTION:Element data read from a vector register designated in an operand part of an instruction are stored successively in a read register 2, and it is then, after being delayed by a buffer register 4 by one-time slot, added to an arithmetic pipeline 5. Further, element data that are designated and read out in an next operand part are successively set in a read register 3 and are inputted into the line 5. An arithmetic result outputted from said pipeline is set in a write register 1, further is written in a vector register designated in the operand part of the instruction. Further, a mask element read from an operand register designated in the mask operand part of the instruction is read out and is set in a register 6, further the output is inputted into the line 5, thereby determining execution of an operation by the logic of the mask element.

PURPOSE:To determine the bank units of vector registers without hindrance to practical use and to make it possible to utilize them in parallel by supplying outputs by bank units to a pipeline arithmetic part via different buses. CONSTITUTION:Between a main memory device which is not shown in the figure and pipeline arithmetic part 6, vector registers #0VR, #1VR...nVR stored with data loaded from the memory device and data of the arithmetic result of arithmetic part 6 are equipped. Then, those vector registers are equipped in four banks, for example, as shown in the figure so that the same one bank unit will be divided; the ''i''-th data and ''i+1''-th data of one vector register are stored in mutually different bank units and outputs by bank units are supplied to the side of arithmetic part 6 via mutually different buses. Consequently, bank units of vector registers are determined without hindrance to practical use and are used in parallel.

Pipeline arithmetic unit

PURPOSE:To obtain a data conversion system which converts the index row of the index sparse vector into a lined-up bit string data of the bit sparse vector

Sparse vector control data conversion system

PURPOSE:To speed the operation up by making it possible to supply reguired data continuously to a pipeline operator at a compound operation time until the compound operation is completed. CONSTITUTION:Pipeline operator 5 operates data sent from data buffer 3-1 for B operand and data buffer 3-2 for C operand. The signal (A request), which requests vector control block 8 to store the operation result into data buffer 6 is issued when a B end signal to indicate the last element of B operand from vector control block 8 is received. When the B end signal and a C end signal to indicate the last element of C operand are received and the processing for the last data is completed, a P end signal to indicate that all operations have been completed is sent.

Vector operation control system

PURPOSE:To carry out the replacement of a memory address in N times overlap for an operator having a low level of processing capacity as compared with an operator having a high level of processing capacity, and as a result, it is satisfactory to virtually carry out the common and same access process from the side of a memory. CONSTITUTION:A system includes operators 12-A and 12-B having the 1:N processing capacity plus a memory 11 consisting of memory registers 11-R0-11-RP. In such system, the address replace emerging at the N-th time is decided to be effective. Thus the operator 12-B scans by N times repetitively a series of element data belonging to the 1st and 2nd memory registers and at the same time, takes N pieces plus the residual element data into a buffer register 21 at the reading side. The result of arithmetic is temporarily stored in a buffer register 22 at the writing side, and then the result of arithmetic corresponding to N pieces of data are stored in the 3rd memory register consecutively and en bloc. The other residual data are stored after the lapse of a prescribed period of time.

Uchida Keiichirou

Papers

Vector data processor

Pipeline arithmetic unit

Sparse vector control data conversion system

Vector operation control system

Vector arithmetic processing method