O
Olli Vainio
Researcher at Tampere University of Technology
Publications - 55
Citations - 425
Olli Vainio is an academic researcher from Tampere University of Technology. The author has contributed to research in topics: Finite impulse response & Digital filter. The author has an hindex of 12, co-authored 55 publications receiving 421 citations. Previous affiliations of Olli Vainio include Tufts University.
Papers
More filters
Journal ArticleDOI
Predictive synchronization and restoration of corrupted velocity samples
TL;DR: In this paper, a cascade predictor structure is proposed for good overall noise attenuation, which is capable of synchronizing and restoring the corrupted and unevenly spaced samples, and a software implementation of the proposed algorithm has been developed and tested on the TMS320C25 signal processor.
Journal ArticleDOI
DSP system integration and prototyping with FPGAS
TL;DR: The fast ASIC prototyping concept based on the use of multiple FPGAs is reviewed in different engineering applications and some future goals are outlined to develop an integrated, multipurpose DSP ASIC prototypes prototyping environment.
Proceedings ArticleDOI
Design of predictive IIR filters via feedback extension of FIR forward predictors
TL;DR: In this paper, a feedback extension scheme for FIR forward predictors is presented, which makes it possible to design IIR predictors with low passband ripple and high stopband attenuation.
Journal ArticleDOI
Design of predictive IIR filters via feedback extension of FIR forward predictors
TL;DR: In this article, a feedback extension scheme for FIR forward predictors is presented, which makes it possible to design infinite impulse response (IIR) predictors with low passband ripple and high stopband attenuation.
Journal ArticleDOI
Processors for generalized stack filters
TL;DR: New processor structures for generalized stack filters are proposed and coder and decoder networks are developed for the mutual transform of binary-weighted and unary- weights codes as the thresholding and addition units of the processors.