When mismatches are present in a dynamic comparator, due to internal positive feedback and transient response, it is always challenging to analytically predict the input-referred random offset voltages since the operating points of transistors are time varying. In this paper, a novel balanced method is proposed to facilitate the evaluation of operating points of transistors in a dynamic comparator. Thus, it becomes possible to obtain an explicit expression for offset voltage in dynamic comparators. We include two types of mismatches in the model: 1) static offset voltages from the mismatch in muCox and threshold voltage Vth and 2) dynamic offset voltage due to the mismatch in the parasitic capacitances. From the analytical models, designers can obtain an intuition about the main contributors to offset and also fully explore the tradeoffs in dynamic comparator design, such as offset voltage, area and speed. To validate the balanced method, two topologies of dynamic comparator implemented in 0.25-mum and 40-nm CMOS technology are applied as examples. Input-referred offset voltages are first derived analytically based on SPICE Level 1 model, whose values are compared with more accurate Monte Carlo transient simulations using a sophisticated BSIM3 model. A good agreement between those two verifies the effectiveness of the balanced method. To illustrate its potential, the explicit expressions of offset voltage were applied to guide the optimization of ldquoLewis-Grayrdquo structure. Compared to the original design, the input offset voltage was easily reduced by 41% after the optimization while maintaining the same silicon area.

Analyses of Static and Dynamic Random Offset Voltages in Dynamic Comparators

A novel time-domain bulk-tuned offset cancellation technique is applied to a low-power high-precision dynamic comparator to reduce its input-referred offset with minimal additional power consumption and delay. The design has been fabricated in a commercially available 0.5-μm process. Measurement results of 10 circuits show a reduction of offset standard deviation from 5.415 mV to 50.57 μV, improved by a factor of 107.1. The offset cancellation scheme does not introduce observable offset or noise, and can achieve fast and robust convergence with a wide range of common mode input. Operating at a supply of 5 V and clock frequency of 200 kHz, the comparator together with the OC circuitry consumes 4.65 μW of power, or 23 pJ of energy per comparison.

A Low-Power High-Precision Comparator With Time-Domain Bulk-Tuned Offset Cancellation

In this paper, we present a survey of recent works in developing neuromorphic or neuro-inspired hardware systems. In particular, we focus on those systems which can either learn from data in an unsupervised or online supervised manner. We present algorithms and architectures developed specially to support on-chip learning. Emphasis is placed on hardware friendly modifications of standard algorithms, such as backpropagation, as well as novel algorithms, such as structural plasticity, developed specially for low-resolution synapses. We cover works related to both spike-based and more traditional non-spike-based algorithms. This is followed by developments in novel devices, such as floating-gate MOS, memristors, and spintronic devices. CMOS circuit innovations for on-chip learning and CMOS interface circuits for post-CMOS devices, such as memristors, are presented. Common architectures, such as crossbar or island style arrays, are discussed, along with their relative merits and demerits. Finally, we present some possible applications of neuromorphic hardware, such as brain–machine interfaces, robotics, etc., and identify future research trends in the field.

Low-Power, Adaptive Neuromorphic Systems: Recent Progress and Future Directions

Self-powered monitoring refers to a signal processing technique where the computational power is harvested directly from the signal being monitored. In this paper, we present the design and calibration of a CMOS event counter for long-term, self-powered mechanical usage monitoring. The counter exploits a log-linear response of the hot-electron injection process on a floating-gate transistor when biased in weak-inversion. By configuring an array of floating-gate injectors to respond to different amplitude levels of the input signal, a complete analog processor has been designed that implements a level counting algorithm, which is widely used in mechanical usage monitoring. Measured results from a fabricated prototype in a 0.5-?m CMOS process demonstrate that the processor can sense, store and compute over 105 usage cycles with an injection limit approaching one single electron per second and with a counting resolution of 5 bits. This paper also presents a calibration algorithm that is used for compensating the variations which arise due to device mismatch, power supply and temperature fluctuations. The maximum current rating of the fabricated analog processor has been measured to be less than 160 nA making it ideal for practical self-powered sensing applications.

Calibration and Characterization of Self-Powered Floating-Gate Usage Monitor With Single Electron per Second Operational Limit

Optimization for offset and kickback-noise in novel CMOS double-tail dynamic comparator: A low-power, high-speed design approach using bulk-driven load

We apply the technique of floating-gate differential injection to a 1.2-GHz CMOS comparator to achieve arbitrary, accurate, and adaptable offsets. The comparator uses nonvolatile charge storage on floating-gate nodes for either offset nulling or automatic programming of a desired offset. We utilize impact-ionized pFET hot-electron injection to achieve fully automatic offset programming. The design has been fabricated in a commercially available 4-metal, 2-poly 0.35-mum CMOS process. Experimental results confirm the ability to reduce the variance of comparator offset by 3600times and to accurately program a desired offset with maximum observed residual offset of 469 muV and standard deviation of 199 mu V. We achieve controlled injection to accurately program the input offset to voltages uniformly distributed from -1 to 1 V. The comparator operates at 1.2 GHz with a power consumption of 3.3 mW.

P.A. Abshire

Papers

A 1.2-GHz Comparator With Adaptable Offset in 0.35- $\mu$ m CMOS