In nanometric technologies, circuits are increasingly sensitive to various kinds of perturbations. Soft errors, a concern for space applications in the past, became a reliability issue at ground level. Alpha particles and atmospheric neutrons induce single-event upsets (SEU), affecting memory cells, latches, and flip-flops, and single-event transients (SET), initiated in the combinational logic and captured by the latches and flip-flops associated to the outputs of this logic. To face this challenge, a designer must dispose a variety of soft error mitigation schemes adapted to various circuit structures, design architectures, and design constraints. In this paper, we describe various SEU and SET mitigation schemes that could help the designer meet her or his goals.

Design for soft error mitigation

Over the last few years, an increasing number of safety-critical tasks have been demanded of computer systems. In this paper, a software-based approach for developing safety-critical applications is analyzed. The technique is based on the introduction of additional executable assertions to check the correct execution of the program control flow. By applying the proposed technique, several benchmark applications have been hardened against transient errors. Fault injection campaigns have been performed to evaluate the fault detection capability of the proposed technique in comparison with state-of-the-art alternative assertion-based methods. Experimental results show that the proposed approach is far more effective than the other considered techniques in terms of fault detection capability, at the cost of a limited increase in memory requirements and in performance overhead.

Soft-error detection using control flow assertions

Pulsed laser single-event upset tests are used to pinpoint and characterize sensitive nodes of circuits and to provide feedback relevant to the development and optimization of radiation-hard designs. The results presented reveal the advantages of incorporating laser evaluation at an early stage into programs described for the development of radiation-hardened parts. A quantitative correlation is observed between the laser single-event upset and single-event latchup threshold measurements and those performed using accelerator-based heavy ion testing methods.

Application of a pulsed laser for evaluation and optimization of SEU-hard designs [CMOS]

This paper investigates an approach to study the effects of upsets on the operation of microprocessor-based digital architectures. The method is based on the injection of bit-flips, randomly in time and location by using the capabilities of typical application boards. Experimental results, obtained on programs running on two different digital boards, built around an 80C51 microcontroller and a 320C50 Digital Signal Processor, illustrate the potentialities of this new strategy.

Predicting error rate for microprocessor-based digital architectures through C.E.U. (Code Emulating Upsets) injection

This paper deals with a software modification strategy allowing on-line detection of transient errors. Being based on a set of rules for introducing redundancy in the high-level code, the method can be completely automated, and is therefore particularly suited for low-cost safety-critical microprocessor-based applications. Experimental results are presented and discussed, demonstrating the effectiveness of the approach in terms of fault detection capabilities.

Experimentally evaluating an automatic approach for generating safety-critical software with respect to transient errors

With the miniaturization, integrated circuits become more en more sensitive to perturbations resulting from the effects of the environment (temperature, radition, EMC, ) This paper describes a test system which facilitates the realization and exploitation of qualification tests for all kind of circuits, from a simple register bench to complex components such as processors

THESIC: A testbed suitable for the qualification of integrated circuits devoted to operate in harsh environment

In this paper, we present software tools for predicting the rate and nature of observable SEU induced errors in microprocessor systems. These tools are built around a commercial microprocessor simulator and are used to analyse real satellite application systems. Results obtained from simulating the nature of SEU induced errors are shown to correlate with ground-based radiation test data.

SEU induced errors observed in microprocessor systems

Artificial Neural Networks have been shown to possess fault tolerant properties. We present the architecture of a neural network designed to process satellite images (SPOT photos). Computer simulations and ground tests performed on a digital implementation of this neural network prove its robustness with respect to bit errors.

Artificial neural network robustness for on-board satellite image processing: results of upset simulations and ground tests

This paper deals with a software modification strategy allowing the on-line detection of transient errors. Being based on a set of rules for introducing redundancy in the high-level code, the method can be completely automated, and is particularly suited for low-cost safety-critical microprocessor-based applications. Experimental results from software and hardware fault injection campaigns are presented and discussed, demonstrating the effectiveness of the approach in terms of fault detection capabilities.

P. Cheynet

Papers

Experimentally evaluating an automatic approach for generating safety-critical software with respect to transient errors

THESIC: A testbed suitable for the qualification of integrated circuits devoted to operate in harsh environment

SEU induced errors observed in microprocessor systems

Artificial neural network robustness for on-board satellite image processing: results of upset simulations and ground tests

System safety through automatic high-level code transformations: an experimental evaluation