Information Theory and Reliable Communication

We survey recent developments in the design of large-capacity content-addressable memory (CAM). A CAM is a memory that implements the lookup-table function in a single clock cycle using dedicated comparison circuitry. CAMs are especially popular in network routers for packet forwarding and packet classification, but they are also beneficial in a variety of other applications that require high-speed table lookup. The main CAM-design challenge is to reduce power consumption associated with the large amount of parallel active circuitry, without sacrificing speed or memory density. In this paper, we review CAM-design techniques at the circuit level and at the architectural level. At the circuit level, we review low-power matchline sensing techniques and searchline driving approaches. At the architectural level we review three methods for reducing power consumption.

https://www.pagiamtzis.com/pubs/pagiamtzis-jssc2006.pdf

Content-addressable memory (CAM) circuits and architectures: a tutorial and survey

Are Power Line Communications (PLC) a good candidate for Smart Grid applications? The objective of this paper is to address this important question. To do so, we provide an overview of what PLC can deliver today by surveying its history and describing the most recent technological advances in the area. We then address Smart Grid applications as instances of sensor networking and network control problems and discuss the main conclusions one can draw from the literature on these subjects. The application scenario of PLC within the Smart Grid is then analyzed in detail. Because a necessary ingredient of network planning is modeling, we also discuss two aspects of engineering modeling that relate to our question. The first aspect is modeling the PLC channel through fading models. The second aspect we review is the Smart Grid control and traffic modeling problem which allows us to achieve a better understanding of the communications requirements. Finally, this paper reports recent studies on the electrical and topological properties of a sample power distribution network. Power grid topological studies are very important for PLC networking as the power grid is not only the information source but also the information delivery system-a unique feature when PLC is used for the Smart Grid.

/pdf/for-the-grid-and-through-the-grid-the-role-of-power-line-u1a0j36lkc.pdf

For the Grid and Through the Grid: The Role of Power Line Communications in the Smart Grid

Quantum cryptography is arguably the fastest growing area in quantum
information science. Novel theoretical protocols are designed on a regular
basis, security proofs are constantly improving, and experiments are
gradually moving from proof-of-principle lab demonstrations to in-field
implementations and technological prototypes. In this paper, we provide
both a general introduction and a state-of-the-art description of the
recent advances in the field, both theoretical and experimental. We start
by reviewing protocols of quantum key distribution based on discrete
variable systems. Next we consider aspects of device independence,
satellite challenges, and protocols based on continuous-variable systems.
We will then discuss the ultimate limits of point-to-point private
communications and how quantum repeaters and networks may overcome these
restrictions. Finally, we will discuss some aspects of quantum
cryptography beyond standard quantum key distribution, including quantum
random number generators and quantum digital signatures.

/pdf/advances-in-quantum-cryptography-47uxe1y6u2.pdf

Advances in quantum cryptography

Internet of Things (IoT) technology has attracted much attention in recent years for its potential to alleviate the strain on healthcare systems caused by an aging population and a rise in chronic illness. Standardization is a key issue limiting progress in this area, and thus this paper proposes a standard model for application in future IoT healthcare systems. This survey paper then presents the state-of-the-art research relating to each area of the model, evaluating their strengths, weaknesses, and overall suitability for a wearable IoT healthcare system. Challenges that healthcare IoT faces including security, privacy, wearability, and low-power operation are presented, and recommendations are made for future research directions.

Internet of Things for Smart Healthcare: Technologies, Challenges, and Opportunities

SUMMARY In-building power lines have often been considered as attractive media for high-speed data transmission, particularly for applications like home networking. In this paper, we develop models for power line channels based both on theoretical considerations and practical measurements. We consider power line channel frequency response and noise models in the 1–30 MHz band and propose a number of power line test channels in which to measure the performance of power line modems. Copyright # 2003 John Wiley & Sons, Ltd.

In‐building power lines as high‐speed communication channels: channel characterization and a test channel ensemble

Delivering milliwatts of wireless power at centimeter distances is advantageous to many existing and emerging biomedical applications It is highly desirable to fully integrate the receiver on a single chip in standard CMOS with no additional post-processing steps or external components This paper presents a 2 $\,\times \,$ 218 ${\rm mm}^{2}$ on-chip wireless power transfer (WPT) receiver (Rx) coil fabricated in 013 $\mu {\rm m}$ CMOS The WPT system utilizes a 145 $\, \times \,$ 145 ${\rm mm}^{2}$ transmitter (Tx) coil that is fabricated on a standard FR4 substrate The on-chip power harvester demonstrates a peak WPT efficiency of $-1847~{\rm dB}$ , ${-2096}~{\rm dB}$ and $-2015~{\rm dB}$ at 10 mm of separation through air, bovine muscle and 02 molar NaCl, respectively The achieved efficiency enables the delivery of milliwatts of power to application circuits while staying below safe power density and electromagnetic (EM) exposure limits

Fully Integrated On-Chip Coil in 0.13 $\mu {\rm m}$ CMOS for Wireless Power Transfer Through Biological Media

The speed at which two remote parties can exchange secret keys over a fixed-length fiber-optic cable in continuous-variable quantum key distribution (CV-QKD) is currently limited by the computational complexity of post-processing algorithms for key reconciliation. Multi-edge low-density parity-check (LDPC) codes with low code rates and long block lengths were proposed for CV-QKD, in order to extend the maximum reconciliation distance between the two remote parties. Key reconciliation over multiple dimensions has been shown to further improve the error-correction performance of multi-edge LDPC codes in CV-QKD, thereby increasing both the secret key rate and distance. However, the computational complexity of LDPC decoding for long block lengths on the order of 10^6 bits remains a challenge. This work introduces a quasi-cyclic (QC) code construction for multi-edge LDPC codes that is highly suitable for hardware-accelerated decoding on a modern graphics processing unit (GPU). When combined with an 8-dimensional reconciliation scheme, the LDPC decoder achieves a raw decoding throughput of 1.72Mbit/s and an information throughput of 7.16Kbit/s using an NVIDIA GeForce GTX 1080 GPU at a maximum distance of 160km with a secret key rate of 4.10x10^{-7} bits/pulse for a rate 0.02 multi-edge code with block length of 10^6 bits when finite-size effects are considered. This work extends the previous maximum CV-QKD distance of 100km to 160km, while delivering between 1.07x and 8.03x higher decoded information throughput over the upper bound on the secret key rate for a lossy channel. The GPU-based QC-LDPC decoder achieves a 1.29x improvement in throughput over the best existing GPU decoder implementation for a rate 1/10 multi-edge LDPC code with block length of 2^{20} bits. These results show that LDPC decoding is no longer the computational bottleneck in long-distance CV-QKD.

/pdf/key-reconciliation-with-low-density-parity-check-codes-for-4mdb7vvd1n.pdf

Key Reconciliation with Low-Density Parity-Check Codes for Long-Distance Quantum Cryptography

Homomorphic encryption (HE) systems enable computations on encrypted data, without decrypting and without knowledge of the secret key. In this work, we describe an optimized Ring Learning With Errors (RLWE) based implementation of a variant of the HE system recently proposed by Gentry, Sahai and Waters (GSW). Although this system was widely believed to be less efficient than its contemporaries, we demonstrate quite the opposite behavior for a large class of applications. We first highlight and carefully exploit the algebraic features of the system to achieve significant speedup over the state-of-the-art HE implementation, namely the IBM homomorphic encryption library (HElib). We introduce several optimizations on top of our HE implementation, and use the resulting scheme to construct a homomorphic Bayesian spam filter, secure multiple keyword search, and a homomorphic evaluator for binary decision trees. Our results show a factor of $10\times$ improvement in performance (under the same security settings and CPU platforms) compared to IBM HElib for these applications. Our system is built to be easily portable to GPUs (unlike IBM HElib) which results in an additional speedup of up to a factor of $103.5\times$ to offer an overall speedup of $1{,}035\times$ .

SHIELD: Scalable Homomorphic Implementation of Encrypted Data-Classifiers

The speed at which two remote parties can exchange secret keys in continuous-variable quantum key distribution (CV-QKD) is currently limited by the computational complexity of key reconciliation. Multi-dimensional reconciliation using multi-edge low-density parity-check (LDPC) codes with low code rates and long block lengths has been shown to improve error-correction performance and extend the maximum reconciliation distance. We introduce a quasi-cyclic code construction for multi-edge codes that is highly suitable for hardware-accelerated decoding on a graphics processing unit (GPU). When combined with an 8-dimensional reconciliation scheme, our LDPC decoder achieves an information throughput of 7.16 Kbit/s on a single NVIDIA GeForce GTX 1080 GPU, at a maximum distance of 142 km with a secret key rate of 6.64 × 10−8 bits/pulse for a rate 0.02 code with block length of 106 bits. The LDPC codes presented in this work can be used to extend the previous maximum CV-QKD distance of 100 km to 142 km, while delivering up to 3.50× higher information throughput over the tight upper bound on secret key rate for a lossy channel. Improvements in the post-processing algorithms for quantum cryptography can extend the secure transmission distance by over 40%. Quantum key distribution protocols rely on the transmission of quantum states, but also on classical post-processing to eliminate errors introduced by imperfect equipment or the interference of an attacker. Over long distances, the requirements of this classical 'reconciliation' processing can become the bottleneck for key exchange. Mario Milicevic and colleagues from the University of Toronto and the University of British Columbia in Canada have developed a high-throughput error correction scheme that increases the potential operating range for quantum key distribution from 100 to 143 km. Their method is fast enough that the rate of key distribution is instead limited by the physical properties of the communication channel.

/pdf/quasi-cyclic-multi-edge-ldpc-codes-for-long-distance-quantum-2cy1b2xz1w.pdf

P. Glenn Gulak

Papers

In‐building power lines as high‐speed communication channels: channel characterization and a test channel ensemble

Fully Integrated On-Chip Coil in 0.13 $\mu {\rm m}$ CMOS for Wireless Power Transfer Through Biological Media

Key Reconciliation with Low-Density Parity-Check Codes for Long-Distance Quantum Cryptography

SHIELD: Scalable Homomorphic Implementation of Encrypted Data-Classifiers

Quasi-cyclic multi-edge LDPC codes for long-distance quantum cryptography