A circuit at the register transfer level is denoted as an RTL circuit. The paper describes a method for extracting the RTL circuit structure from the circuit formal description, using the I-path concept. The way of representing the RTL circuit structure by a labelled directed graph where nodes represent components and arcs represent connections between them, is presented. Labels identifying the component type are attached to the nodes, and other labels are attached to arcs to identify attributes of connections. It is shown, how the graph theory algorithms can be used to derive the information about the accessibility of circuit components, i.e., the existence of I-paths between them, and the sequences of control and clock signals which must be generated to transfer the information along the existing I-paths. >

I-path analysis

A symbolic simulation methodology that can be used to verify a set of standard scan-path-based, ad hoc, and boundary-scan design-for-testability (DFT) rules is proposed, and a DFT rule checker, TDRC (testability design rule checker), that uses this methodology is described. In this methodology, symbolic tokens are used to represent the types of signals applied to the primary inputs of the circuit, and, in a process analogous to simulation, these tokens are propagated through the circuit using a set of simulation rules. A check is then made to verify that the required tokens have been propagated to each scan element and that only allowed tokens have reached particular element and circuit ports. The proposed simulation methodology differs from previous path-tracing approaches in that symbolic tokens are propagated to the output of an object, possibly in modified form, depending on the other tokens reaching both the inputs and the logical function of the object. TDRC has been successfully used to identify real problems in real ASIC (application-specific integrated-circuit designs). >

TDRC-a symbolic simulation based design for testability rules checker

The test protocol for a serial scan design comprises the serial scan-in, parallel measure & capture, and serial scan-our operations. Through symbolic simulation of the protocol, compliance with scan design rules can be verified. For example, simulation of the scan-in operation should establish an arbitrary known state in all sequential cells within the design. A cell whose state is not controllable represents a design rule violation. This approach is both more flexible and more robust than previous work, and addresses current issues with the integration of internal scan and boundary scan. Further, the approach links the tasks of design rule checking and the formatting of the output of Automatic Test Pattern Generation (ATPG) into a scan test program. This approach has been applied successfully to a wide variety of designs, up to 700 K gates.

A simulation-based protocol-driven scan test design rule checker

An automatic design-for-testability (DFT) rule checker that can be used during early design stages at the register-transfer level is described. The system uses expert-system technology to check the correspondence of a rule set to a register-transfer level description of the design. In addition, it runs quickly and interactively, supports hierarchical design by checking subcircuits and groups of subcircuits, and provides concrete references about possible rule violations in the circuit and advice on how to eliminate them. The system accepts arbitrary DFT rule sets as input and analyzes highly integrated circuits hierarchically. Its output provides the location of rule violations or, if there are no violations, DFT descriptions of the circuit and the analysis protocol. >

A rule-based design-for-testability rule checker

An AI constraint network-based approach to bed-of-nails DFT for digital circuit design

A description is given of ESTA, an expert system for the automation of design for testability (DFT) verification. The system takes descriptions written in a conventional hardware description language as input, translates them into a intermediate Prolog form and checks whether they comply either with the level sensitive scan design (LSSD) DFT method of B. Eichelberger and T.W. Williams (1977) or the built-in logic block observation (BILBO) DFT techniques of B. Konemann et al. (1979). >

P. Prinetto

Papers

ESTA: an expert system for DFT rule verification