Journal ArticleDOI
ESTA: an expert system for DFT rule verification
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TLDR
A description is given of ESTA, an expert system for the automation of design for testability (DFT) verification that takes descriptions written in a conventional hardware description language as input, translates them into a intermediate Prolog form and checks whether they comply with the level sensitive scan design DFT techniques.Abstract:
A description is given of ESTA, an expert system for the automation of design for testability (DFT) verification. The system takes descriptions written in a conventional hardware description language as input, translates them into a intermediate Prolog form and checks whether they comply either with the level sensitive scan design (LSSD) DFT method of B. Eichelberger and T.W. Williams (1977) or the built-in logic block observation (BILBO) DFT techniques of B. Konemann et al. (1979). >read more
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Proceedings ArticleDOI
I-path analysis
TL;DR: It is shown, how the graph theory algorithms can be used to derive the information about the accessibility of circuit components, i.e., the existence of I-paths between them, and the sequences of control and clock signals which must be generated to transfer the information along the existing I- Paths.
Proceedings ArticleDOI
TDRC-a symbolic simulation based design for testability rules checker
TL;DR: A symbolic simulation methodology that can be used to verify a set of standard scan-path-based, ad hoc, and boundary-scan design-for-testability (DFT) rules is proposed, and a DFT rule checker, TDRC (testability design ruleChecker), that uses this methodology is described.
Proceedings ArticleDOI
A simulation-based protocol-driven scan test design rule checker
TL;DR: This work links the tasks of design rule checking and the formatting of the output of Automatic Test Pattern Generation into a scan test program, which is both more flexible and more robust than previous work, and addresses current issues with the integration of internal scan and boundary scan.
Journal ArticleDOI
A rule-based design-for-testability rule checker
TL;DR: An automatic design-for-testability (DFT) rule checker that can be used during early design stages at the register-transfer level is described and provides concrete references about possible rule violations in the circuit and advice on how to eliminate them.
Journal ArticleDOI
An AI constraint network-based approach to bed-of-nails DFT for digital circuit design
J. Bowen,D. Bahler,Ajay Dholakia +2 more
TL;DR: An approach to implementing on-line DFT advice systems which can give designers the kind of feedback that would be provided by test engineers on an AI programming technology called constraint networks is presented.
References
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Book ChapterDOI
A framework for representing knowledge
TL;DR: The enormous problem of the volume of background common sense knowledge required to understand even very simple natural language texts is discussed and it is suggested that networks of frames are a reasonable approach to represent such knowledge.
A framework for representing knowledge
TL;DR: The authors describes frame systems as a formalism for representing knowledge and then concentrates on the issue of what the content of knowledge should be in specific domains, arguing that vision should be viewed symbolically with an emphasis on forming expectations and then using details to fill in slots in those expectations.
Journal ArticleDOI
Design for Testability—A Survey
TL;DR: The different techniques of design for testability are discussed in detail, including techniques which can be applied to today's technologies and techniques which have been recently introduced and will soon appear in new designs.
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