We examine the current performance and future demands of interconnects to and on silicon chips. We compare electrical and optical interconnects and project the requirements for optoelectronic and optical devices if optics is to solve the major problems of interconnects for future high-performance silicon chips. Optics has potential benefits in interconnect density, energy, and timing. The necessity of low interconnect energy imposes low limits especially on the energy of the optical output devices, with a ~ 10 fJ/bit device energy target emerging. Some optical modulators and radical laser approaches may meet this requirement. Low (e.g., a few femtofarads or less) photodetector capacitance is important. Very compact wavelength splitters are essential for connecting the information to fibers. Dense waveguides are necessary on-chip or on boards for guided wave optical approaches, especially if very high clock rates or dense wavelength-division multiplexing (WDM) is to be avoided. Free-space optics potentially can handle the necessary bandwidths even without fast clocks or WDM. With such technology, however, optics may enable the continued scaling of interconnect capacity required by future chips.

Device Requirements for Optical Interconnects to Silicon Chips

The various arguments for introducing optical interconnections to silicon CMOS chips are summarized, and the challenges for optical, optoelectronic, and integration technologies are discussed. Optics could solve many physical problems of interconnects, including precise clock distribution, system synchronization (allowing larger synchronous zones, both on-chip and between chips), bandwidth and density of long interconnections, and reduction of power dissipation. Optics may relieve a broad range of design problems, such as crosstalk, voltage isolation, wave reflection, impedence matching, and pin inductance. It may allow continued scaling of existing architectures and enable novel highly interconnected or high-bandwidth architectures. No physical breakthrough is required to implement dense optical interconnects to silicon chips, though substantial technological work remains. Cost is a significant barrier to practical introduction, though revolutionary approaches exist that might achieve economies of scale. An Appendix analyzes scaling of on-chop global electrical interconnects, including line inductance and the skin effect, both of which impose significant additional constraints on future interconnects.

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Rationale and challenges for optical interconnects to electronic chips

The microprocessor system in portable electronic devices often has a time-varying computational load which is comprised of: (1) compute-intensive and low-latency processes, (2) background and high-latency processes, and (3) system idle. The key design objectives for the processor systems in these applications are providing the highest possible peak performance for the compute-intensive code (e.g., handwriting recognition, image decompression) while maximizing the battery life for the remaining low performance periods. If clock frequency and supply voltage are dynamically varied in response to computational load demands, then energy consumed per process can be reduced for the low computational periods, while retaining peak performance when required. This strategy, which achieves the highest possible energy efficiency for time-varying computational loads, is called dynamic voltage scaling (DVS).

A dynamic voltage scaled microprocessor system

An apparatus may include a semiconductor chip and a fluidics assembly. The semiconductor chip has an array of wells and an array of sensors and each sensor of the array of sensors is in fluid communication with a well of the array of wells. The fluidics assembly is located on top of the semiconductor chip and is configured to deliver fluids to the semiconductor chip. The fluidics assembly includes a flow expansion chamber configured to introduce the fluids, an outlet portion configured to pipe out the fluids, and a flow chamber portion. The flow chamber portion is configured to allow the fluids to flow from the flow expansion chamber to the outlet portion and to allow the fluids to interact along the way with material in the array of wells. The flow expansion chamber has a curved wall at the top or bottom so that the height of the flow expansion chamber at the center is less than at the walls that restrict the fluids to the left and right.

Methods and apparatus for measuring analytes using large scale fet arrays

Peer-to-Peer (P2P) reputation systems are essential to evaluate the trustworthiness of participating peers and to combat the selfish, dishonest, and malicious peer behaviors. The system collects locally-generated peer feedbacks and aggregates them to yield the global reputation scores. Surprisingly, most previous work ignored the distribution of peer feedbacks. We use a trust overlay network (TON) to model the trust relationships among peers. After examining the eBay transaction trace of over 10,000 users, we discover a power-law distribution in user feedbacks. Our mathematical analysis justifies that power-law distribution is applicable to any dynamically growing P2P systems, either structured or unstructured. We develop a robust and scalable P2P reputation system, PowerTrust, to leverage the power-law feedback characteristics. The PowerTrust system dynamically selects small number of power nodes that are most reputable using a distributed ranking mechanism. By using a look-ahead random walk strategy and leveraging the power nodes, PowerTrust significantly improves in global reputation accuracy and aggregation speed. PowerTrust is adaptable to dynamics in peer joining and leaving and robust to disturbance by malicious peers. Through P2P network simulation experiments, we find significant performance gains in using PowerTrust. This power-law guided reputation system design proves to achieve high query success rate in P2P file-sharing applications. The system also reduces the total job makespan and failure rate in large-scale, parameter-sweeping P2P Grid applications.

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PowerTrust: A Robust and Scalable Reputation System for Trusted Peer-to-Peer Computing

The authors present the architecture of a general-purpose broadband-ISDN (B-ISDN) switch chip and, in particular, its novel feature: the weighted round-robin cell (packet) multiplexing algorithm and its implementation in hardware. The flow control and buffer management strategies that allow the chip to operate at top performance under congestion are given, and the reason why this multiplexing scheme should be used under those circumstances is explained. The chip architecture and how the key choices were made are discussed. The statistical performance of the switch is analyzed. The critical parts of the chip have been laid out and simulated, thus proving the feasibility of the architecture. Chip sizes of four to ten links with link throughput of 0.5 to 1 Gb/s and with about 1000 virtual circuits per switch have been realized. The results of simulations of the chip are presented. >

Weighted round-robin cell multiplexing in a general-purpose ATM switch chip

This paper describes a dual delay-locked loop architecture which achieves low jitter, unlimited (modulo 2/spl pi/) phase shift, and large operating range. The architecture employs a core loop to generate coarsely spaced clocks, which are then used by a peripheral loop to generate the main system clock through phase interpolation. The design of an experimental prototype in a 0.8-/spl mu/m CMOS technology is described. The prototype achieves an operating range of 80 kHz-400 MHz. At 250 MHz, its peak-to-peak jitter with quiescent supply is 68 ps, and its jitter supply sensitivity is 0.4 ps/mV.

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A semidigital dual delay-locked loop

A memory system architecture/interconnect topology that includes at least one point-to-point link between a master, and at least one memory subsystem. The memory subsystem includes a buffer device coupled to a plurality of memory devices. The memory system may be upgraded through dedicated point-to-point links and corresponding memory subsystems. The master communicates to the plurality of memory devices in each memory subsystem through the respective buffer device via each point-to-point link.

Memory system including a point-to-point linked memory subsystem

Advances in IC fabrication technology, coupled with aggressive circuit design, have led to exponential growth of IC speed and integration levels. For these improvements to benefit overall system performance, the communication bandwidth between systems and ICs must scale accordingly. Currently, communication links in various applications approach Gbps data rates. These applications include computer-to-peripheral connections, local area networks, memory buses, and multiprocessor interconnection networks. Designers are concerned that these links will soon reach the fundamental limits of electrical signaling. In this article, we examine the limitations of CMOS implementations of highspeed links and show that the links' performance should continue to scale with technology. To handle the interconnects' finite bandwidth, however requires more sophisticated signaling methods. CMOS circuits, typically slower than circuits implemented in nonmainstream technologies, are particularly attractive for common applications because of their lower cost. The overall system cost is further reduced when signaling components are implemented as macro cells, integrated on the same die with a microprocessor or signal processing block.

High-speed electrical signaling: overview and limitations

A multiphase receiver to compensate for intersymbol interference in the sampling of an input signal includes a first integrating receiver to integrate and sample data of the input signal on a first phase of a clock and a second integrating receiver to integrate and sample data of the input signal on a second phase of the clock. The multiphase receiver also includes an equalization circuit to adjust integration by the first integrating receiver dependent on a result of integration of data previously received by an integrating receiver distinct from the first integrating receiver, and to adjust integration by the second integrating receiver dependent on a result of integration of data previously received by an integrating receiver distinct from the second integrating receiver.

Stefanos Sidiropoulos

Papers

Weighted round-robin cell multiplexing in a general-purpose ATM switch chip

A semidigital dual delay-locked loop

Memory system including a point-to-point linked memory subsystem

High-speed electrical signaling: overview and limitations

Integrating receiver with precharge circuitry