P
Pang-Yen Tsai
Researcher at TSMC
Publications - 42
Citations - 584
Pang-Yen Tsai is an academic researcher from TSMC. The author has contributed to research in topics: Layer (electronics) & Epitaxy. The author has an hindex of 13, co-authored 42 publications receiving 583 citations.
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Patent
Stack SiGe for short channel improvement
TL;DR: In this paper, a semiconductor structure includes a first compound layer comprising an element, and a first impurity having a first-impurity concentration; and a second compound layer consisting of an element and an impurity of a same conductivity type as the first one, where the second impurity has a second-level impurity concentration.
Proceedings ArticleDOI
High density 3D integration using CMOS foundry technologies for 28 nm node and beyond
Jing-Cheng Lin,W. C. Chiou,Kuo-Nan Yang,Hun-Hsien Chang,Y.C. Lin,E.B. Liao,Hung Jeng-Nan,Y.L. Lin,Pang-Yen Tsai,Yi-Chun Shih,T.J. Wu,W.J. Wu,F.W. Tsai,Y.H. Huang,T. Y. Wang,C.L. Yu,C.H. Chang,M. F. Chen,Shang-Yun Hou,C. H. Tung,S.P. Jeng,Doug C. H. Yu +21 more
TL;DR: Technology challenges and solutions in the development and fabrication of high-density three dimensional (3D) chip integration structures have been investigated and test vehicles have been designed to develop and optimize the processes, structures, as well as to evaluate the performance, yield and reliability of the 3D integration scheme.
Patent
MOSFET Device With Localized Stressor
TL;DR: In this article, a treatment is performed on the stress-inducing layer such that a reaction is caused with the first semiconductor material and the second semiconductor materials is forced lower into the stressinducing layer.
Patent
Method of manufacturing strained-silicon semiconductor device
TL;DR: In this article, a method for fabricating a strained-silicon semiconductor device to ameliorate undesirable variation in selectively grown epitaxial film thickness was proposed, where a dummy pattern appropriate to the proposed layout was created, incorporated into the mask design, and then implemented on the substrate along with the originally-proposed component configuration.
Patent
PMOS transistor with discontinuous CESL and method of fabrication
TL;DR: In this paper, a transistor has a discontinuous contact etch stop layer comprising: a substrate having a surface, a gate dielectric on the surface of the substrate, a spacer along a sidewall of the gate and a gate electrode, a source and a drain formed on opposite sides of said gate and said gate electrode respectively, the source and drain defining a channel region having a channel length extending substantially from said source to said drain, in the substrate therebetween, and a contact ensembles.