Tze-Liang Lee

TL;DR: In this article, the authors describe a FinFET with a substrate, a fin structure on the substrate and a drain in the fin structure, a channel between the source and the drain, and a gate over the gate dielectric layer.

TL;DR: This is the smallest fully functional 128Mb HD FinFET SRAM (with single fin) test-chip demonstrated with low Vccmin for 16nm node and provides 2X logic density and 2X speed gain over 28nm HK/MG planar technology.

TL;DR: In this article, a semiconductor structure is defined, and a stressor has a tilted sidewall on a side adjacent the gate electrode and a second layer has a third lattice constant substantially different from the first and the second lattice constants.

TL;DR: In this article, a strained channel MOSFET device with improved charge mobility and method for forming the same, the method including providing a first gate with a first semiconductor conductive type on a substrate; forming a first strained layer with first type of stress on said first gate; and, forming a second strained layer, with a second type of stressed on said second gate.

TL;DR: The 5nm platform technology successfully passed qualification with consistently high yielding 256Mb HD/HC SRAM, and large logic test chip consisting of CPU/GPU/SoC blocks, on schedule for high volume production in 1H 2020.